Papers by Keyword: Threshold Voltage

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Abstract: In addition to the well-known bias temperature instability (BTI) phenomena, recently, it has been revealed that SiC MOSFETs show another instability during high-frequency repetitive switching between VGS(L) and VGS(H), referred to as gate-switching instability (GSI). This study shows the increase in switching energy caused by gate-switching instability VGS(th) drift as key performance parameters in electric power conversion systems, especially, when operating in hard-switching mode. A new methodology based on double pulse test was applied at each readout. The results highlighted the significance of the degradation mechanism through its impact on hard-switching applications with high-switching frequency. Therefore ruggedness against GSI plays a pivotal role in the long-term reliable operation of SiC MOSFET devices to ensure durable and efficient power conversion systems.

Abstract: We use novel three-level pulse sequences, where the intermediate level is either above or below the threshold voltage, to investigate gate switching instability (GSI) in 4H-SiC-MOSFETs. Results with sequences with an intermediate level above the threshold voltage (V_th) seem to falsify the hypothesis that trapped holes remaining at the interface after switching to the on-state, are the root cause for GSI, as was described in [1, 2]. Fast switching applications may cause negative transient pulses on the gate electrode during the off-state. Results with sequences with an intermediate level below threshold show that such transients may cause an increased V_th-drift. Introducing a delay between the transient and the turn-on of the transistor in such pulse sequences, does not mitigate the effect of a negative transient on the V_th-drift.

Abstract: Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

Abstract: In this paper, the effect of a non-linear dielectric gate stack on the short-circuit performance of a 1.2 kV SiC MOSFET was analyzed through TCAD simulations. Starting from the TCAD model of a commercial 1.2 kV, its standard gate oxide was replaced with a stack formed by oxide and a non‑linear dielectric, characterized by a temperature dependent permittivity. This variation on temperature can be exploited to reduce the current conducted during short-circuit events, lowering the temperature reached through the device by about 30%, without affecting its static and dynamic performance.

Abstract: This article presents an innovative approach to achieve a high channel mobility for 4H-SiCp-MOSFET via dielectric-semiconductor interface engineering involving atomic layer deposition(ALD) of ultrathin B₂O₃ and SiO₂ stacks. The application of ultrathin boron oxide via ALD introducesa highly manufacturable solution for the passivation of SiC interface. The interface states near valenceband reduces the channel mobility for SiC p-MOSFETs and increases the threshold voltage. Theintroduction of ultrathin B₂O₃ interlayer reduces the threshold voltage and improves the field effectmobility to 12.60 cm²/Vs while the p-MOSFET without the interlayer provides the mobility of 8.91cm²/Vs. This work also includes the optimization of the post-deposition annealing (PDA) conditionsspecific to ultrathin B₂O₃ and bulk SiO₂ dielectric stack to obtain high field effect channel mobilityfor SiO₂/SiC p-MOSFETs.

Abstract: Gate oxide reliability is a challenge in SiC MOSFETs particularly due to the presence of high electric field in the dielectric during device operation and blocking, and SiC/SiO₂ interfaces suffer from a high density of traps and defects that can cause charge trapping and threshold voltage shift. Highly accelerated gate bias testing can be used for testing gate field effects on device reliability/stability, but care must be taken that the high acceleration biases do not invoke failure mechanisms that fall outside of normal device operation conditions. In this work, we attempt to address that aspect of high voltage gate tests in terms of threshold voltage instability and perform a comparative analysis between commercially available planar and trench SiC MOSFETs.

Abstract: In this paper we study the feasibility of the design/fabrication of a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints of the depth of the P+ implantation. The P+ doping profile is obtained using a Monte Carlo implantation simulation. The calculation used a drift-diffusion approach. The JFET aims to achieve a threshold voltage of-3V. We found that this constraint in concomitance with the proposed structure limits the breakdown voltage to approximately 200V. This is the result of a premature breakdown induced by short channel effects, namely Drain Induced Barrier Lowering (DIBL). However, a negative increase in the gate bias represses this short channel effect and improves the breakdown voltage to roughly 1800V. At this gate bias, the breakdown is induced by reaching the critical field strength of 4H-SiC at the gate P+/N junction, which causes avalanche generation of carriers. In addition, we have calculated the dependence of the threshold voltage on the drift doping and pillar width. This work also shows the vulnerability of the design to random fluctuation in the doping profile.

Abstract: Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.

Abstract: To scale digital circuits, symmetric threshold voltages (V_th) for n-type transistors (NMOS) and p-type transistors (PMOS) are important. One step towards this in silicon carbide (SiC) is selecting a p-doped polysilicon (pPolySi). This implementation has been shown in this work with V_th being evaluated by five different methods. Furthermore, operating temperatures up to 500 °C and their impact on V_th were investigated. It has been successfully demonstrated that elevated temperature shifts V_th of both transistor types towards 0 V, whereas changing the gate electrode from n-doped PolySi (nPolySi) to pPolySi shifts V_th of both transistor types to more positive values. Both effects are complementary for the PMOS, reaching V_th below 4 V.