Papers by Keyword: Threshold Voltage

Abstract: Different material thickness with medium and high dielectric constant can impact the performance and reliability of high electron mobility transistor device. With varying the thickness of the passivation layer, the effect of it towards the device performance is still unclear. Two different insulator layers with a medium dielectric and a high dielectric constant namely Aluminium Nitride and Hafnium Oxide are used as passivation layer in AlGaN/GaN HEMT. Both material performance was simulated via COMSOL software by varying the thickness and the drain current output were compared. The passivation layer thickness of 10nm at V_ds=6 V and V_gs=5 V, HfO₂ outperforms AlN with the output drain current of 39 mA compared to 35 mA respectively. It was observed that HfO₂ can attain higher threshold voltage, V_th as compared to the AlN because of the influence of its material properties that shows a direct proportional relationship between V_th and dielectric constant. Using high dielectric constant material like HfO₂, we observe the ON-voltage gradually decreases as the thickness of the passivation layer increased. Out of all the thickness simulated for HfO₂ and AlN, 10nm produced the highest drain current output instead of layer thickness of 20nm.

Abstract: We supply a hypothesis that explains threshold voltage (V_th) drift under dynamic bipolar gate stress in SiC-MOSFETs, postulating that ionized donor-like interface traps in the lower half of the bandgap, give rise to an increased internal electric field at each rising edge of a gate voltage pulse. The enhancement of the internal electric field may be viewed as a V_th -reduction, and we devised different experiments to assess this V_th -reduction. Comparing V_th -drift rate using different pulse shapes in dynamic bipolar gate stress tests, we estimated a temporary V_th -reduction in the order of 15 V within 200 ns after the rising edge. Measuring the drain-source current peak 200 ns after the rising edge of a rectangular pulse, gives an estimate for the V_th -reduction of 5.5 V. To resolve this discrepancy, we postulate that in inversion, positive traps are effectively screened such that the impact on the channel is spatially restricted and smaller than the channel length. Channel current will only flow where positive charges induce a percolation path between drain and source, reducing the apparent V_th -reduction in the current based measurement.

Abstract: Germanium (Ge) is envisioned as a suitable channel candidate for field-effect transistors (FET). Properties of Ge such as high carrier mobility, compatibility with Si and adaptability with high-k materials makes it comparable to silicon. This paper presents a detailed design of a 30 nm Ge based FinFET by parameter optimization using Silvaco software. Poisson and Schrodinger equation is used to come up with an analytical quantum model. The quantum model is developed based on theory of a double gate (DG) FET but the final design is a trigate (TG) device since they are more scalable. The quantum attributes of DG MOSFET are acquired by adopting the coupled Poisson–Schrodinger equation with the aid of the variational approach. The ratio of channel length (L_C) to fin height (H_fin) to fin thickness (t_fin) is 4:2:1. The channel length is taken as the gate length (L_G) although they are slightly differ mathematically due to side diffusion of the implanted ions. Simulation results show that physical parameters such as dimensions influence electrical characteristics of the device such as threshold voltage (V_TH). Much focus is on optimization of the on/off current ratio (I_ON/_OFF) and V_TH performances. I_ON/_OFF ≈ 10⁶ is achieved at carrier concentration in the range 1 × 10¹⁸ ≤ n_d ≤ 1.22 × 10¹⁸ and in this scenario, V_TH = 0.4V . Systematical investigation is presented using IV characteristics to demonstrate the sensitivity or how critical design parameters of Ge FinFET are to the device’s figure of merits. Device performs well at low voltages but breaks down at higher drain voltages (V_DS ≥ 4V). Gate source voltages (V_GS) range between 0.05V≤ V_GS ≤ 1V and conductance is dependent on it. Effects of DIBL, which is around 0.031, and velocity saturation are studied to determine how they can be suppressed during the design process.

Abstract: We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Abstract: In this work, the impact of channel implantations (IMP) on the electrical characteristics of SiC n-and p-MOSFETs and analog SiC-CMOS operational amplifiers (OpAmp) is investigated. For this purpose, MOSFETs and Miller OpAmps with and without IMP were fabricated and electrically characterized from room temperature up to 350°C. For devices with IMP the absolute values of the threshold voltages of n-and p-MOSFETs were reduced by 1.5 V and the mobility of the n-MOSFET was increased from 13 to 23 cm2/Vs whereas the mobility of the p-MOSFET remained constant at 6 cm2/Vs. For the resulting OpAmp with IMP, the common-mode input voltage range as well as the open loop gain was increased by 1.5 V and 4 dB compared to non-implanted devices. This improvement was observed across the entire analyzed temperature range from room temperature up to 350°C.

Abstract: We report the physical and electrical characterization of the inversion layer carrier and the shallow interface trap sites with n-and p-channel SiC-MOSFET in terms of high temperature electronics. This work proposes a physical model that explains the difference between I_d-V_g measurement result and calculation result supposing the ideal condition with Pao and Sah double ideal in room temperature. The measurement at 500°C confirmed our model so that inversion carrier were thermally excided, they could not be easily trapped by shallow trap sites, and I_d-V_g measurement result approached the ideal condition.

Abstract: Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (V_T) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for V_T stability.

Abstract: This paper presents a study of the 1.2kV UMOSFETs with dual shielding regions. Numerical simulations demonstrate the importance of including dual shielding regions to achieve low specific on-resistance and high breakdown voltage. The optimized structure has a low specific on-resistance (R_on,sp) of 2.19 mΩ-cm², high breakdown voltage of 1470 V, low specific reverse transfer capacitance (C_gd,sp) of 17 pF/cm2 and excellent high-frequency figure-of-merit (HF-FOM) of 37 fs.

Abstract: In this work we have studied the electro-optical effect of two types of ferronematic nanoparticles. The first sample doped with magnetic material Fe₃O₄ and the second sample doped with a ferroelectric material SbSI. The difference in the two types of material that has been vaccinated led to different values of electro-optic properties because of the different susceptibility of materials. We have noticed that the material SbSI was more responsive to the applied electric field due to the nature of the constituent material (electric material) than the Fe₃O₄ ferromagnetic. The response time for the material SbSI is less than the response time of the ferromagnetic Fe₃O₄, that led to make the material SbSI best in the optical switch applications.

Abstract: In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.