Papers by Keyword: Transconductance

Abstract: SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO₂ interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Abstract: This paper presents an analytical model of various electrical parameters for an ultra thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT). The model works for all the regions of operation of the nanowire transistor without using any fitting parameter. The surface potential is derived based on the solutions of Poisson’s and current continuity equations by using appropriate boundary conditions. The Pao–Sah double integral was used to obtain the drain current, transconductance and drain conductance. The results obtained from analytical model are validated by comparing with GENIUS 3D TCAD simulations. The simplicity of the model makes it appropriate to be a SPICE compatible model.

Abstract: This paper presents an analytical model for ultra scaled symmetric double gate (SDG) nanowire junctionless field effect transistor (JLFET), which includes charge quantization in all the regions of operation. This model is based on a first-order correction for the confined energies obtained by solving the Schrodinger’s equation. The model is able to predict the quantum mechanical effects (QME) on the surface potential, drain current and transconductance for a highly doped and extremely thin silicon layer of thickness down to 4nm. The results obtained are validated by comparing with GENIUS 3D TCAD quantum simulations.

Abstract: The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

Abstract: In this paper, the digital and analog performance for Double Material Gate Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (DM SG MOSFET) has been analyzed. A detailed study of DM SG MOSFET is performed for different channel length ratio's. The comparison analysis on surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried with respect to the silicon dioxide and hafnium dioxide based device. It has been found from the simulation results that HfO₂ dielectric used DM SG TFET provides better performance than SiO₂ dielectric used DM SG TFET. Also it has been observed from the presented results that the transconductance is 45.32 at 1:3 channel length ratio for DG SG MOSFET.

Abstract: In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

Abstract: We investigate a cascode configuration of a normally-on SiC-Buried Gate Static Induction Transistor (SiC-BGSIT) and Si-MOSFET as an alternative switching device of the SiC-MOSFET. It is shown that the transconductance of our cascode device is much higher than that of commercial SiC-MOSFETs while the switching speed is much faster than that of normally-off SiC-BGSITs. The origin of the fast switching speed in this cascode configuration is discussed in terms of a simulated reverse transfer capacitance.

Abstract: In this paper, arealizationcurrent controlled current conveyor transconductance amplifier (CCCCTA)is presented astheactiveelement.Thisdesignwas based on aCMOStechnology of AMIS 0.35μm (MOSIS).The PSPICE simulation was used to study the performances of the proposed circuit. It was found that the abilities of differential-pair CCCII circuit and Electronically current-tunable (EOTA) can be achieved using the supply voltages of ±1.5volts and the transconductance gain of the circuit can be linearly tuned.

Abstract: We investigated the effect of an Al₂O₃ insertion layer in the gate insulator to make V_th higher and to improve the transconductance G_m in a SiC-MOSFET. Insertion of the Al₂O₃ layer successfully enlarged Vth by about 4 V. The Vth difference sub-threshold Id-Vg characteristics measured by sweeping the gate voltage bi-directionally indicates that insertion of the Al₂O₃ layer decreased the number of traps of electrons in the gate insulator. Due to this decrease, device reliability in long-term operation was improveed by smaller Vth shift in PBTI. It was also found that the insertion of the Al₂O₃ layer improved G_m by two times. Using this gate insulator, we succeeded in fabricating 600 V 20 A-class vertical SiC DMOSFETs with a high Vth (>5 V) and low Ron of 3 mΩcm².