Papers by Keyword: VLSI

Abstract: In the present nanoscale regime, mixed carbon nanotube bundles (MCBs) are considered to be highly promising interconnect options. This research paper introduces a spatially arranged mixed carbon nanotubes (CNTs) bundle (MCB), wherein single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) occupy equal halves in the MCB. An equivalent single conductor (ESC) model for MCB is employed to analyze the interconnect performances in terms of signal transmission delay and dynamic crosstalk delay at different technology nodes (i.e., 32nm, 22nm, and 16 nm). Encouragingly, a significant reduction in signal transmission delay and dynamic crosstalk induced delay are observed at 32 nm technology node. It is observed that at 32 nm technology node, the propagation delay and crosstalk induced delay significantly improves by 29.40% and 55.53%, respectively, compared to 22 nm technology node and 187.88% and 185.94%, respectively, compared to 16 nm technology node. The improvement in interconnect performances can primarily be attributed to the improvement in the number of conducting channels inside the MCB at 32 nm, which greatly impacted the interconnect parasitics such as quantum resistance, quantum capacitance, kinetic inductance etc.

Abstract: The performance of the SiO₂ MOSFET-based absorber as a solution to arching within transmission lines (used for RF signal transportation) has been realized and analyzed at 28 GHz using the reflected signal from the R_X branch of 5G massive MIMO base station. The reflected signal from the receiver (R_X) branch of base stations may lead to interference, thus creating a performance reducing condition (arching) within the transmission lines. For optimum performance in the 5G regime, the SiO₂ MOSFET has been used to solve the problem of arching within the transmission line under large field intensities of a standing wave resulting from the impedance. The SiO₂ MOSFET-based absorber has been observed for a reflectivity of -79.5 dB and a rectification efficiency greater than 17 %

Abstract: This paper presents system performance indices for a class-B power amplifier using Double-Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It also presents a comparative analysis of three power amplifiers using different switching devices, i.e. Bipolar Junction Transistor (BJT), MOSFET, and DG MOSFET. The MOSFET used in this research work is based on Silicon for n-MOSFET and SiO₂ has been used as oxide layer. These power amplifiers are also being designed and simulated to test the speed and time (taken for each of these power amplifiers) to get the output signal when an input signal is applied. A comparison of these three power amplifier circuits is taken in the tabular form to conclude which power amplifier circuit performs better regarding its switching speed and the time. Switching speed relates with the time taken to amplify the signal, which is the same as its time to amplify the signal to a specific gain. Settling time for these three types of power amplifiers have also been tested and presented for the performance of these power amplifiers.

Abstract: This research work designs a power amplifier with the use of Silicon-based Double-Gate (DG) MOSFET. It is a novel device used to amplify the input signal of an audio signal, etc. This research paper provides information on the problem identification in the existing models and its design objectives with its design constraints. It also reduces crossover distortion due to DG MOSFET instead of BJTs and MOSFETs in the class-B power amplifier. This is a low-power device for the mA range using SiO₂ as a dielectric material.

Abstract: The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO₂ which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.

Abstract: The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300 K. The doping concentration for the electrons and holes is maintained to be 1Χ10¹⁹cm^-3 for the entire electronic simulator. The simulation results show that using La₂O₃ along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50 nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.

Abstract: One of the most challenging problems in developing the astrionics of the recoverable orbital ADDAHORSE microcapsule is represented by the power and size constraints which require an extreme degree of miniaturization. The size, mass and power requirements of the electronic and computing (astrionics) on-board control and command equipment can be conveniently reduced by designing an Application Specific Integrated Circuit (ASIC) which integrates sensors, autopilot logic, drivers, RF communication and interface subsystems in a single, combined SoC (System-on-Chip). The feasibility of such a device is discussed here within the bounds of the ADDAHORSE project which was proposed for structural funding in Romania in 2014. This study was conducted by the Center for Innovation and Development in the Exploration of Space (CIDES) in the emerging Făgăraș facility of the future Făgăraș Space Center in Romania.

Abstract: Silicon Carbide metal-oxide-semiconductor field effect transistor (4H-SiC MOSFET) can be considered as the next revolution in power electronics applications. However, a wide market introduction of 4H-SiC MOSFET requires a special focus on device reliability and simplicity of use to replace Silicon switches in existing applications. This paper describes STMicroelectronics (STM) approach to define methodology and design solutions able to guarantee the end-users and to drive their choice toward 4H-SiC MOSFET as an ideal power component.

Abstract: This paper propose an efficient VLSI architecture of camera distortion correction based on neural camera distortion model (NCDM). Different from conventional imaging method uses over two kind models to correct the camera and lenses distortions, the NCDM uses a single model to correct at once the geometry distortion and the unsymmetrical manufacture errors. The NCDM with four neurons perform the wide-angle distortion correction, results show that the maximal corrected error in a whole image is less than 1.1705 pixels, and that the MSE approaches 0.1743 between the corrected and ideal results. The distortion correction by NCDM is 429x more accurate than the conventional approach. The chip size of NCDM is 1.51 x 1.51 mm^2 that contains 126K gates by using TSMC 90 nm CMOS technology process. As working at 240Mhz, this architecture can correct 30 frames and Full-HD resolution video per second. Results show that the maximal corrected error in a whole image is less than 1.4 pixels, and that the mean square error approaches 0.0376 between the corrected and ideal results.

Abstract: Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.