Papers by Keyword: Verilog Language

Abstract: At present, because more embedded image compressions are single, various compression methods have not transplant to embedded equipment. In this paper, A BP neural network based image compression methods have been proposed. The neural network is trained more and more, and obtained a set of weights and thresholds usefully. Then, use the FPGA to achieve, In the FPGA, using the framework of soft-core Nios Ⅱ way. Ultimately, compression program written using Verilog and burned into the FPGA. Experiments show that the system has the advantages of high compression ratio, small size, and can stable operation.