Papers by Keyword: Vertical Junction Field Effect Transistor (VJFET)

Abstract: Operation of parallel-connected 4H-SiC VJFETs from SemiSouth was measured and modeled using numerical simulations. The unbalanced current waveforms in parallel-connected VJFETs were related to spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The physical device structure was reconstructed based on SEM analysis, electrical characterization, and device simulations. The two hypothetical critical design parameters that were studied with respect to spread were the p-gate doping profile (Case 1) and the emitter doping (Case 2). Variation in both parameters could be related to variation in the emitter breakdown voltage, the on-state characteristics, and the threshold voltage of the experimental devices. The switching performance of the parallel-connected JFETs was measured using a single gate driver in a double pulse test and compared with simulations. In both investigated cases a very good agreement between measurements and simulations was obtained. The modeling of the transient performance relies on good reproduction of transfer characteristics and circuit parasitics.

Abstract: An optically controlled power switch based on 4H-SiC Trenched and Implanted Vertical JFETs (TIVJFET) was developed that comprises three parts: an LED light-source driver, light-triggered integrated gate buffer driver, and vertical high power normally-off switch. The light-triggered integrated gate buffer driver includes a photodiode and four stages of low voltage 4H-SiC TIVJFETs, which are hybrid integrated. Optically gated power switching was experimentally demonstrated with a maximum switching frequency of about 50 kHz, the system performance limiting factors were clearly identified and experimentally confirmed, and ways to substantially increase the switching frequency were shown. From calculations, based on realistically possible system parameters values, it could be seen that a maximum switching frequency around 1 MHz is theoretically possible with a proper choice of light source, detector, and buffer transistor parameters.

Abstract: Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.

Abstract: A new silicon carbide (SiC) enhancement-mode lateral channel vertical junction fieldeffect transistor (LC-VJFET), namely “source inserted double-gate structure (SID-gate) with a supplementary highly doped region (SHDR)”, was proposed for achieving extremely low power losses in high power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LCVJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20 % reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75 % ~ 95 % reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.

Abstract: Physics-based analytical models are seen as an efficient way of predicting the characteristics of power devices since they can achieve high computational efficiency and may be easily calibrated using parameters obtained from experimental data. This paper presents an analytical model for a 4H-SiC Enhancement Mode Vertical JFET (VJFET), based on the physics of this device. The on-state and blocking behaviour of VJFETs with finger widths ranging from 1.6+m to 2.2+m are studied and compared with the results of finite element simulations. It is shown that the analytical model is capable of accurately predicting both the on-state and blocking characteristics from a single set of parameters, underlining its utility as a device design and circuit analysis tool.