Papers by Keyword: Wafer

Abstract: Light capturing is an essential part of many optical devices such as solar cells. This study aimed at modifying surface reflectivity of silicon solar wafers to improve light trapping. A simple and easily controllable etching technique was used to achieve this objective. The surface topography of silicon wafers was modified by etching a controllable pyramid structure on these surfaces. Potassium hydroxide (KOH) solution was used to etch the silicon surface; the concentrations of KOH were 1mol/L and 2mol/L at temperatures 50°C and 70°C and a varying etching time of 15 and 30 minutes. The surface morphology of the wafer was analyzed by optical microscopy. The activation energy for the reaction was shown to be 42.2 kJ that is very near the value indicated by previous investigators. A texturization mechanism was also advanced using a new parameter that monitors the progressive changes in the diameter of the pyramids. This analysis shows a general increase in the sizes with reduction at certain intervals that can be attributed to the difference in etching rates of the crystal family planes.

Abstract: As semiconductor processing technologies continue to advance, semiconductor wafers are becoming more densely packed and intricate, resulting in a higher incidence of surface imperfections. Therefore, it is crucial to detect these defects early and accurately classify them to pinpoint the root causes of the defects in the manufacturing process, ultimately leading to improved yield. Therefore, defect detection is critical in the industrial production of monocrystalline silicon. This study employs deep learning techniques to propose a framework for detecting defects on silicon wafers, focusing on optimizing the hyperparameters of support vector machines (SVM). Three methods were utilized to fine-tune the SVM parameters: Bayesian optimization, grid search, and random search techniques. This study demonstrates how selecting optimal values for SVM parameters can lead to better classification. Additionally, real manufacturing data were utilized to evaluate the performance of the proposed SVM classifier, with a comparison to state-of-the-art techniques in the field. By using deep features from ResNet 101 and a support vector machine, this work achieves 74.5% accuracy in identifying wafer defects without employing any optimization technique. However, the performance of the model was further improved by utilizing the random search optimization technique, which yielded the best result among the three optimization techniques tested, with an accuracy of 88.1%.

Abstract: The front opening unified pod (FOUP) is a packing box for contamination control for semiconductor wafer transport. As the wafer fabrication process developes towards nanoor atom level, the semiconductor wafer storage device should advance from the particle prevention function into the airborne molecular contamination (AMC) removal function. Therefore, it is necessary to design/redesign a function for removing AMC or moisture inside the FOUP. This study used the design of leading diffuser tubes in the FOUP and pores in the surfaces of diffuser tubes to generate gas diffusion. This is to achieve a uniform distribution of the wafer surface velocity field and a uniform dehumidification function of the wafer surface. Based on the analysis results, when circular diffuser tubes are introduced in the FOUP and the intake air flow was set at 0.2-0.3 m³/hr, the interlayer wafer surface in the FOUP could achieve uniform distribution of velocity field. As a result, the humidity difference among various zones of wafer surface could be reduced, and the yield and quality of the wafer cutting process could be controlled.

Abstract: Wafer scratching from handling and processing can impact the performance of devices grown on a substrate. Knowledge of process conditions and modeling of scratches on wafers can be used to elucidate the root cause of scratches so that they can be eliminated.

Abstract: Polishing of Silicon Carbide (SiC) seed crystals and substrates to achieve an extremely smooth, level surface, and an optically clear finish takes many surface finishing steps with very long processing times producing a significant amount of slurry waste and utilizing numerous lapping and polishing machines. This paper presents a newly developed cost-efficient SiC polishing process which reduces these operations to two surface finishing steps for achieving an optically clear finish on monocrystalline SiC material where the same size of diamond abrasives for lapping and polishing steps allows to carry out stock removal lapping and polishing processes on a single platform (machine) without concern of cross-contamination and making it as a very cost-efficient and high-throughput polishing process for SiC seed crystals and substrates.

Abstract: Spin-coating process is one of the important parts in the fabrication of semiconductor integrated circuits (IC). Numerical simulations and experiments based on Fluent were carried out, including discussing geometric parameters of spin-coating pallet that affect wafer deformation. The numerical results indicated that under the same effect of vacuum negative pressure, when wafer-supporting stage diameter (D) was smaller than 30mm, the wafer deformation was mainly warpage deformation; and when D was greater than 45mm, spin-coating pallet deformation affected the wafer deformation increasingly and downwarping deformation was occurred at the wafer edge. At the same exit velocity, the deformation around the wafer center and the vacuum degree were both increased with the increase of vacuum suction diameter (d). When the area of the wafer-supporting stage was 1/2~3/5 of the wafer and d was about 3mm, the wafer deformation was the smallest.

Abstract: Silicon Carbide (SiC) abrasive machining solid particulates is one of the key engineering materials in the continuous development of wafer technology. Analysis of its packing behaviour is important to ensure the highest quality in the ingot cutting process to produce silicon PV wafers. One of the parameters that is monitored is the amount of fine particles present during the cutting operation and the subsequent separation technologies to recycle the material to reduce cost and allow environmental sustainability. This study presents results showing that with increasing circularity, less fines remain in the slurry suspension which is expressed as the percentage of total volume of particles in the slurry mixture. Furthermore, the work has gathered that there is a strong relationship between the % fines removed and the average diameter of the particles. An analysis of the relationship between the actual % fines remaining as a function of particle diameter reveals that the % fines remaining decreases as the particle diameter increases and this behavior correlates well with a power law equation. This agrees with a model of the fishhook effect during particle separation in a mini-hydrocyclone expressed as an equation raised to the fourth power.

Abstract: The flatness of a silicon carbide wafer in terms of bow and warp is the result of the combination of factors both material and process related. Sub-surface damage (SSD) from the wafering process steps can be considered as a thin film under compressive stress on the wafer surface. SSD is generally decreased with each subsequent processing step after the multiwire saw. Single-sided process steps can produce very different levels of SSD on opposing wafer surfaces, leading to high bow and warp values. The present study investigates the effects of SSD on wafer flatness at various process steps as well as methods to minimize shape effects due to SSD during and after processing.

Abstract: Raman spectroscopy is a well established non-destructive tool for determining crystal polytypes, strain/stress, electronic properties and material quality in SiC. Here we report on the application of ultrafast Raman imaging to a SiC wafer, allowing 870,908 spectra to be collected from a 2 inch 4H-SiC wafer, in 75 minutes. Analysis of the acquired data enabled us to locate and investigate defects and surface contamination and also allowed stress in the wafer to be characterised.

Abstract: the paper introduced the bare silicon crystal how to become a wafer .then, it told the processing of wafers to produce integrated circuits .Today, most integrated circuits (ICs) are made of silicon. every integrated circuit is tested and functional and formed a dies. At last , the article explain feature size and the number of gross die per wafer (DPW).