Papers by Keyword: Wafer Bonding

Abstract: A review of the specific characterisation techniques developed and customized for SmartSiC™ substrates is given. A focus is made on thermal characterization of this engineered structure as well as its beneficial features with regards to bipolar degradation.

Abstract: A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.

Abstract: During making the surface acoustic wave devices and integrated circuit hybrid integrated electronics, it needs to put the piezoelectric crystal and silicon wafer bonding together. By selecting a certain wavelengths of UV curing adhesive, then exposing with 300-436nm wavelength of exposure machine, 8mm×8mm bonding chips are got. Bonding LiNbO3, quartz and silicon wafer respectively, measured maximum shear force is 116.2 N and 117.9 N with shear force test machine. The fracture energy is 5.831 J/m² measured by crack-opening method test LiNbO3 bonding chips. The results show that piezoelectric crystal and silicon wafer bonding interface level off and the bonding of the middle layer thickness for about 3 microns observed the bonding section with SEM.

Abstract: This paper focus on the Oxygen plasma surface treatment affect on the bonding strength. In shearing force tests , total 10 samples were tested. Through the shear force tests, it indicates that moderate exposure to O₂ plasma could increase the bonding strength to some extent. Then the AFM tests results shows that the MR-I 9100M coating topography is about 14 nm, while after Oxygen plasma treatment the topograhy decrease to 7.9 nm. And the MR-I 9150M coating topography is about 5.5 nm, while after Oxygen plasma treatment the topograhy decrease to 4.6 nm. By AFM tests, it can be found that the Oxygen plasma surface treatment cause the decrease of the surface roughness. And it puts forward another possible explanation for the Oxygen plasma treatment can improve the bonding strength.

Abstract: Si wafers were directly bonded to 6H-SiC wafers without the formation of an intermediate layer. Heterojunctions of n-Si/n-SiC and p-Si/n-SiC exhibited ohmic and rectifying characteristics, respectively, as expected based on their band lineups. Band bending of Si at the bonded interface was observed for Si/semi-insulating 6H-SiC heterointerfaces. This band bending can be explained by either heterojunction formation based on Anderson’s model or the existence of negative charge with a density of ~2 × 10¹⁰ cm⁻² at the Si/SiC interface.

Abstract: The influence of GBs contained in the channel of MOS-FETs - fabricated in thin SOI layers - is demonstrated. The drain current measured at room temperature increases about 50 times for nFETs and about 10 times for pFETs, respectively, as compared to reference devices. The observations might be interpreted as a strong increase of the mobility of charge carriers. Moreover, the observed stepwise changes of the drain current at 5 K may point to Coulomb blockades.

Abstract: In this paper, we report on a novel direct wafer bonding technique; Si (111) wafers to polycrystalline silicon carbide carrier wafers. The purpose of this work is to provide a platform for 3C-SiC epitaxial growth above the wafer bonded Si (111) wafers. We have demonstrated reduced wafer bow, confirmed by optical microscopy together with a digital camera. 3C-SiC epitaxial layers have been grown by conventional chemical vapor deposition techniques above Si/SiC structures. All of these 3C-SiC epitaxial layers are highly crystalline in nature. In the future, the realization of thick, bow-free 3C-SiC layers suitable for power device fabrication is achievable.

Abstract: This paper describes the physical and electrical properties of a p-n Si/on-axis SiC vertical heterojunction rectifier. A thin 400nm p-type silicon layer was wafer-bonded to a commercial on-axis SiC substrate by room temperature hydrophilic wafer bonding. Transmission electron microscopy was used to identify the crystallographic orientation as (0001)SiC//(001)Si and to reveal an amorphous interfacial layer. Electrical tests performed on the p-n heterodiodes revealed that, after an additional 1000oC anneal, the rectifier exhibit remarkably low leakage current (10nA/cm2 at an anode voltage of V=-6V), improved on-resistance due to bipolar injection and a turn-on voltage close to the p-n heterojunction theoretical value of 2.4V.

Abstract: Wet activation is a very important step in silicon direct wafer bonding process and a optimized activation process is desirable to improve the surface hydrophilicity. Therefore the pivotal parameters of activation process were investigated which were volume ratio, holding time and treat temperature. A orthogonal experiment array was designed to reveal the effects of these parameters and the experiment results were analyzed by range analysis method. The analysis results indicted among those three parameters, everyone had intimidate relationship with surface hydrophilicity, which was indexed by contact angle. And higher concentration, longer holding time and higher treating temperature in possible value range were more desirable. Based on these conclusions, optimized activation process was desigened using which void-free bonding was realized.

Abstract: Current work describes development, testing and verification of a single wafer megasonic cleaning method utilizing a transducer design that meets the extreme particle neutrality, Particle Removal Efficiency (PRE), and repeatability requirements of production scale wafer bonding and other applications requiring extremely low particle levels.