Papers by Keyword: e-Beam Lithography

Abstract: This paper present a new approach for fabricating 3D micro structures based on the elevated structures. The new fabrication method involves combinations of several basic techniques, but a key enabling techniques for the successful development of the fabrication process is combining the photolithography with e-beam lithography processes to create 3-D structures

Abstract: A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that case a voltage bias applied across the source and drain contact of a Hall bar MOSFET will mostly fall across the contacts (and not across the channel) and therefore magneto-transport measurements become challenging. However, from a physical point of view, the study of MOSFET nanostructures in the low electron density regime is very interesting (impurity limited mobility [1], carrier interactions [2,3] and spin-dependent transport [4]) and it is therefore important to come up with solutions [5,6] that work around the problem of a high contact resistance in such devices (c.f. Fig. 1 (a)).

Abstract: We demonstrate the fabrication and the electrical transport properties of single crystalline 3C silicon carbide nanowires (SiC NWs). The growth of SiC NWs was carried out in a chemical vapor deposition (CVD) furnace. Methyltrichlorosilane (MTS, CH3SiCl3) was chosen as a source precursor. SiC NWs had diameters of less than 100 nm and lengths of several μm. For electrical transport measurements, as-gown SiC NWs were prepared on a highly doped silicon wafer, pre-patterned by a photo-lithography process, with a 400 nm thick SiO2 layer. Source and drain electrodes were defined by e-beam lithography (EBL). Prior to the metal deposition (Ti/Au : 40 nm/70 nm) by thermal evaporation, the native oxide on SiC NWs was removed by buffered HF. The estimated mobility of carriers is 15 cm2/(Vs) for a source-drain voltage (VSD) of 0.02 V. It is very low compared to that expected in bulk and/or thin film 3C-SiC. The electrical measurements from nanowire-based field effect transistor (FET) structures illustrate that SiC NWs are weak n-type semiconductor. We have also demonstrated a powerful technique, a standard UV photo-lithography process, for fabrication of SiC nanowires instead of using EBL process.

Abstract: We report on simple techniques for extracting the electrical properties of 1-dimensional semiconductor nanowires using standard ultraviolet (UV) photo-lithography instead of e-beam lithography (EBL), which is a commonly used technique for the fabrication of nanoscale electrical devices. For electrical transport measurement the gallium nitride nanowires (GaN NWs) were prepared by a horizontal hot-wall chemical vapor deposition (CVD) with metallic Ga and NH3 gas for Ga and N sources, and GaN nanowire field effect transistor (FET) structures on a 8×8 mm2 silicon wafer were fabricated by ordinary 2-mask photo-lithography processes. The estimated carrier mobility from the gate-modulation characteristics is on the order of 60 ∼ 70 cm2/V⋅s. We found that our approach is a powerful and simple technique to extract the electrical properties of semiconductor nanowires. The material characteristics of GaN nanowires are also discussed.

Abstract: It has recently been demonstrated that it is possible to produce a pristine surface layer on a lapped sapphire substrate by depositing a thin film of aluminum and subjecting it to an appropriate thermal treatment. This process also shows promise for the fabrication of nanopatterned sapphire by pre-patterning the aluminum metal prior to thermal conversion to sapphire. We have explored two distinct patterning processes: a dual layer photoresist e-beam lithography technique for fabricating arbitrarily shaped aluminum structures, and a novel, non-conventional mask-liftoff method involving nanoporous anodized aluminum oxide, useful for patterning very large scale arrays of sub-micron aluminum dots or posts. Our work is focused on refining the fabrication process and investigating the morphological stability of such metal nanostructures during conversion to sapphire.

Abstract: In this paper, we report a method for determining the residual thickness of resist layer during e-beam lithography processes. The method is based on the energy dispersive x-ray spectroscopic (EDS) measurements on a silicon substrate deposited with a PMMA layer. The PMMA layer acts as the resist layer in e-beam lithography. From a calibration test, an empirical relationship is established between the EDS signal, electron energy, and PMMA film thickness. Form this empirical relationship the residual PMMA layer thickness after e-beam exposure and developing can be determined within an accuracy of 83%, which is very important to the subsequent etching processes. An important feature of the proposed method is that its lateral resolution depends only on the focused e-beam spot size and can be in the order of nm. With such resolution, the thickness of the resist layer under few nm line width can be measured. The proposed method to estimate the residual resist layer thickness plays a vital role in nano-fabrication or nano-patterning based on e-beam lithography technology.