Researches on Design and Implementations of Two 2-Bit Predictors

Abstract:

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High-performance superscalar processors, which can be used in building base-stations of cell phones and cloud-based web servers, rely heavily on aggressive branch predictors to avoid stalls no matter the branch is taken or not. Dynamic branch predictor which is based on the historical records of the previously executed branches always outputs good performance. Two-bit predictor discussed in this paper is one of the most popular ones that always practically employed. This paper demonstrates two implementations of two-bit predictors. Using BTB to process solo conditional branches is the first one, which is normally used. Other categories of branch instructions may results in several bubbles as the penalty. While the other implementation employs BTB dealing with all kinds of branch instructions, generating target addresses without any delay cycle. Simulation results show that the second implementation has much better performance than the former one. It decreases the mis-prediction rate from 12.26% to 11.48%, and also has much higher prediction accuracy on indirect jumps. With these results, we have our predictor re-designed accordingly and implemented successfully in superscalar processors.

Info:

Periodical:

Edited by:

Elwin Mao and Linli Xu

Pages:

241-246

DOI:

10.4028/www.scientific.net/AEF.1.241

Citation:

L. Zhang et al., "Researches on Design and Implementations of Two 2-Bit Predictors", Advanced Engineering Forum, Vol. 1, pp. 241-246, 2011

Online since:

September 2011

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