Design and Implementation of a 12-Bit 100MS/s ADC

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In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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Edited by:

Mohamed Othman

Pages:

1507-1510

Citation:

X. N. Fan et al., "Design and Implementation of a 12-Bit 100MS/s ADC", Applied Mechanics and Materials, Vols. 229-231, pp. 1507-1510, 2012

Online since:

November 2012

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$38.00

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