A Digitally Controlled Oscillator for ADPLL Application


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In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication. This new type of oscillator uses MOS varactor arrays to moderating the output frequency, through the using of digitally Sigma-Delta technology, we can get more precise resolution , and through using three modes progressively working way can make this kind of structure easily implement in process.



Edited by:

Mohamed Othman




X. L. Wu et al., "A Digitally Controlled Oscillator for ADPLL Application", Applied Mechanics and Materials, Vols. 229-231, pp. 1515-1518, 2012

Online since:

November 2012




[1] Hosseini, A. Gharaee, H. Optimum quad band DCO in DS method for WCDMA transmitter in 90nm CMOS. IEEE International Conference on Semiconductor Electronics, pp.45-48, (2008).

DOI: https://doi.org/10.1109/smelec.2008.4770274

[2] R.B. Staszewski, John Wallberg, et al. All-Digital PLL and GSM/EDGE Transmitter in 90nm CMOS. ISSCC Dig. Tech. Papers, p.315–317, Feb. (2005).

DOI: https://doi.org/10.1109/isscc.2005.1493996

[3] Wei Liu, Wei Li, et al, A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO. IEEE Journal of Solid-State Circuits, Vol. 45, pp.314-321, Feb. (2010).

DOI: https://doi.org/10.1109/jssc.2009.2038127

[4] Sang-Sun Yoo, Jeong-Ho Park, et al, The variations of osillation freqeuncy according to the oscillation amplitudes in DCO. IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), pp.1-4, (2010).

DOI: https://doi.org/10.1109/edssc.2010.5713724

[5] Xueyi Yu, Yuanfeng Sun Li Zhang, et al, A 1GHz Fractional-N PLL Clock Generator with Low-OSR Modulation and FIR-Embedded Noise Filtering, ISSCC Dig. Tech. Papers, p.346–348, Feb. (2008).

DOI: https://doi.org/10.1109/isscc.2008.4523199