Authors: Lun Ma, Xiang Dong Wu
Abstract: It is required that an ADC for sampling broadband signal directly has high sampling rate, and this will make the sampling accuracy decrease and difficult to be realized. This paper introduces an idea that using multi-channel and low rate ADCs performs sampling broadband signal, then presents a novel method of utilizing adaptive beam forming technique to recover complete bandwidth of the broadband signal. Application of this method can implement both low rate sampling and high accuracy; in addition, it is robust to channel delay and other errors. The result of processing the simulated data has verified the effectiveness of this method.
308
Authors: Li Cheng, Jiao Xu, Yi Xin Zhang, Ning Yang
Abstract: This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.
1820
Authors: Xiang Ning Fan, Hao Zheng, Yu Tao Sun, Xiang Yan
Abstract: In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.
1507
Authors: Hui Yong Sun, Peng Cao
Abstract: The Time-Interleaved ADC(TIADC) is an effective method for implement ultra high-speed data acquisition. However, the errors of channel mismatch are seriously degrade the signal-to-noise ratio of the system, such as Time-skew error, Gain error and Offset error. This paper have done some researches and analysis, and given the modeling of the three channels mismatch. What's more, it also given a detailed analysis of error and the method of measure it, derived the formula of signal to noise and distortion ratio(SINAD) and spurious free dynamic range(SFDR). All of them provide a reference for the tolerance range of TIADC channel mismatch error. Meanwhile, the result of this paper has provided a theoretical basis for eliminating TIADC channel mismatch error.
978
Authors: Sheng Zhu, Jun Xu, Wen Jia, Hai Long Li, Sha Li, Meng Meng Wu, Bo Yi
Abstract: In this paper, it gives a proposal for OCT/VT (optical current / voltage transformer) signals acquisition and processing. This project is used in smart grid, which needs high precision but low EMI. The OCT/VT use fiber to transform signals. It is insulating, susceptible to EMI, and there is no electromagnetic saturation phenomenon. Thus it can fulfill the requirement of smart grid. The project contains four parts: PD and amplification, ADC sampling, digital signals processing and storage, data transmission from PCB board to computer via USB. Compared with other similar methods, this system can provide faster processing speed and higher accuracy. The system measuring range is 0-1000A (OCT) after shunt, and 0-1000V (OVT) after divider, both meet the 0.2S industry standard.
1808