Design of a Communication Interface between the Controller and the Galvanometer


Article Preview

In a laser marking system, a laser marking controller should be designed to control several galvanometers through a certain interface using a certain protocol, such as the XY2-100 or SPI. The selection of the protocol depends on the configuration of the laser marking system. Using different protocols makes the controller design provide two types of interfaces. If different protocols have their own physical interfaces, the circuit becomes more complicated. In order to decrease the number of physical interfaces and ensure the protocol compatibility at the same time, two protocol signal generator modules based on FPGA are provided and the output signals of the two modules share the same physical interface, and only one of them can be chosen according to a flag set by users. This design makes the circuit simpler and decreases the design cost.



Edited by:

Abdel Hamid Ismail Mourad and József Kázmér Tar




J. C. Wei et al., "Design of a Communication Interface between the Controller and the Galvanometer", Applied Mechanics and Materials, Vol. 527, pp. 269-272, 2014

Online since:

February 2014




* - Corresponding Author

[1] D. Castells-Rufas, O. Vila-Closas, J. Carrabina, Design of a Multi-Soft-Core based Laser Marking Controller. In: 2012 International Conference on Reconfigurable Computing and FPGAs. IEEE, Cancun(2012).


[2] Information on http: /www. camtech. com.

[3] Information on http: /www. scanlab. de/link/zh/4919151#4919151.

[4] Information on http: /www. newson. be/files/TD_XY2-100_R0703. pdf.

[5] F. Leens, An Introduction to I2C and SPI Protocols. IEEE Instrumentation and Measurement Magazine. (2009) pp.8-13.

[6] D. Buell, T. El-Ghazawi, K. Gaj, et al., Guest Editors' Introduction: High Performance Reconfigurable Computing. Computer. (2007) pp.23-27.


[7] P. Li, J. Lan, K. Jang: Survey of Research on FPGA-Based Partial Reconfiguration Technology. Journal of Information Engineering University. 10(2009) 98-101. (in Chinese).

[8] B. Fan, Q. Chang, Dynamically reconfigurable system of FPGA based on DSP, Information and electronic engineering. 8(2010) 123-127. (in chinese).

[9] Joseph J. F. Cavanagh: Verilog HDL: Digital Design and Modelling. CRC Press, (2007).