Model Checking Formal Verification Methodology for Virtual Channel NoCs

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The increasing complexity of System on a Chip (SOC) using Network on a Chip (NoC) results in significant increases in traditional verification times. Formal methods fully prove design properties, without deadline vs. coverage compromises, hence tremendously reducing time to market. In this work we use the CONNECT NOC to illustrate our new white box formal verification methodology. We develop constraints and assertions for properties verification. Our methodology is faster than the current methods; it also uncovered key gaps in current practices. In addition, our assertion checkers can be reused both in simulation and as monitors on silicon.

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Edited by:

Mahir Dursun

Pages:

30-37

Citation:

S. Agamy et al., "Model Checking Formal Verification Methodology for Virtual Channel NoCs", Applied Mechanics and Materials, Vol. 850, pp. 30-37, 2016

Online since:

August 2016

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$38.00

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