Design of Ternary Clocked Adiabatic Synchronous Reversible Counter

Abstract:

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Based on the study of synchronous counter and adiabatic circuits, a new design scheme of ternary adiabatic synchronous reversible counter is proposed. According to the theory of three essential circuit elements, circuit structure of four-bit ternary adiabatic synchronous reversible counter is realized by using NMOS transistors with different thresholds and cross-storage structure and combining with the principle of energy recovery. Computer simulation results indicate that the designed circuits have correct logic function. Compared with traditional CMOS counter, the average power consumption of circuits saves up to 67.5%.

Info:

Periodical:

Edited by:

Xingui He, Ertian Hua, Yun Lin and Xiaozhu Liu

Pages:

154-159

DOI:

10.4028/www.scientific.net/AMM.88-89.154

Citation:

F. N. Mei and P. J. Wang, "Design of Ternary Clocked Adiabatic Synchronous Reversible Counter", Applied Mechanics and Materials, Vols. 88-89, pp. 154-159, 2011

Online since:

August 2011

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$35.00

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