Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

Abstract:

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In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

Info:

Periodical:

Advanced Materials Research (Volumes 108-111)

Edited by:

Yanwen Wu

Pages:

625-630

DOI:

10.4028/www.scientific.net/AMR.108-111.625

Citation:

Y. B. Wu et al., "Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes", Advanced Materials Research, Vols. 108-111, pp. 625-630, 2010

Online since:

May 2010

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Price:

$35.00

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