FPGA Based Low Power ROM Design Using Capacitance Scaling

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An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

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Periodical:

Edited by:

Katsuyuki Kida

Pages:

471-474

DOI:

10.4028/www.scientific.net/AMR.1082.471

Citation:

M. Bansal et al., "FPGA Based Low Power ROM Design Using Capacitance Scaling", Advanced Materials Research, Vol. 1082, pp. 471-474, 2015

Online since:

December 2014

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$35.00

* - Corresponding Author

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