Block Treatment of Multi-Layer Wafers for the Development of a Numerical Model of a 300mm Batch Heat Treatment Furnace


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Of all the processing stages for wafers, interior temperature distribution in thermal treatment furnaces has a great influence on wafer properties. Therefore, internal temperature distribution is a key factor for operating a furnace. However, it is practically impossible to directly measure temperatures within the furnace, and consequently the need for a reliable numerical model to analyze temperature distribution is becoming increasingly urgent. Exact modeling of the processing is very difficult because the structure of the furnace used for thermal treatment is very complex, with large numbers of Si wafers stacked within. Therefore, simplified modeling is necessary. The modeling strategy of the present study is to reduce the radiation calculation domain and simplify the model by replacing the wafer stack region with a single block. It is necessary to determine the vertical and horizontal effective thermal conductivities of the block to reflect radiation heat transfer between wafers. In this study, calculations were performed through numerical experimentation, using r k as the heat transfer coefficient in the direction of the radius, and v k for the vertical direction. Using these calculated property values, the temperature distribution within a 300mm thermal treatment furnace can be obtained.



Advanced Materials Research (Volumes 15-17)

Edited by:

T. Chandra, K. Tsuzaki, M. Militzer and C. Ravindran




E. Y. Ko and K. W. Yi, "Block Treatment of Multi-Layer Wafers for the Development of a Numerical Model of a 300mm Batch Heat Treatment Furnace", Advanced Materials Research, Vols. 15-17, pp. 537-542, 2007

Online since:

February 2006




[1] Badwell : Journal of the Electrochemical Society, Vol. 139(1992)., p.524-p.532.

[2] Badwell : AIChE Journal Vol. 38(1992), p.926-p.938.

[3] Yong-Hui Fan, Taiqing Qiu : Int. J. Heat Mass Tranfer, Vol. 41, No. 11, (1998), pp.1549-1557.

[4] S. Hirasawa, S. Keida, T. Watanabe, T Torii, T. Takagaki, and T. Uchino : IEEE Transactions on Semiconductor Manufacturing, VOL. 6, NO. 3(1993).

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