Structural Optimization of Ground Vias for 3D ICs
Nowadays, IC manufacturing meet the challenges of physical limits, through silicon via(TSV) technology has increasingly become the focus of the microelectronics industry due to its shorter wiring route, better signal integrity, larger bandwidth, lower power consumption and smaller packaging size. In this paper, the transmission performance of TSV was analyzed and the impact of ground vias number, diameter and pitch with TSV on TSV transmission performance. A design of experiment (DOE) was established to investigate the impact of different ground vias parameter combinations on the transmission of TSV and the range analysis of the experiment results was executed. Based on the DOE, two regression equations were formed to estimate the electrical performances of TSV. From the two equations, the structure parameters were optimized, the S11 and S21 results of optimization parameter combination reduced 0.4dB and 0.15dB, respectively.
Zhengyi Jiang, Shanqing Li, Jianmin Zeng, Xiaoping Liao and Daoguo Yang
C. Q. Li and X. L. Kuang, "Structural Optimization of Ground Vias for 3D ICs", Advanced Materials Research, Vols. 189-193, pp. 1472-1475, 2011