Collar TEOS Integrity of Deep Trench DRAM Capacitor with a Vertical Parasitic NMOSFET

Abstract:

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An adequate measurement metrology to nondestructively verify the integrity of dielectric gap-fill in a deep trench (DT) capacitor of deep-submicron DRAM product was proposed. Because of the geometric structure in the DT capacitor, the vertical cylindrical electrode isolator approximately provides a parasitic NMOSFET. Through the electrical measurement, people can analyze these drain-to-source electrical characteristics. Some of most valuable device parameters, threshold voltage (Vt) and mobility (un), correlate to the interface integrity and the surface roughness between silicon substrate and gap-fill oxide (or liner oxide). In other words, as these values are obtained, the degradation level of this interface or gap-fill quality can be clarified. Indirectly, the charge storage quality of this capacitor, avoiding the leakage path, is able to be improved with the process modification.

Info:

Periodical:

Advanced Materials Research (Volumes 314-316)

Edited by:

Jian Gao

Pages:

2385-2388

DOI:

10.4028/www.scientific.net/AMR.314-316.2385

Citation:

M. C. Wang and H. C. Yang, "Collar TEOS Integrity of Deep Trench DRAM Capacitor with a Vertical Parasitic NMOSFET", Advanced Materials Research, Vols. 314-316, pp. 2385-2388, 2011

Online since:

August 2011

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Price:

$35.00

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