Design of High-Speed and Low-Power Two-Channel Pipeline ADC
This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.
Liangchi Zhang, Chunliang Zhang and Zichen Chen
L. Cheng et al., "Design of High-Speed and Low-Power Two-Channel Pipeline ADC", Advanced Materials Research, Vols. 328-330, pp. 1820-1823, 2011