Design of High Speed and Parallel Compression System Used in the Big Area CCD of High Frame Frequency

Abstract:

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According to the area CCD camera of characteristics, such as high resolution capacity and high frame frequency, this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly, according to the work principle of the area CCD, FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly, with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip, real time image compression and the high speed area CCD are realized. Finally, by detecting the analog signal of the area CCD output, the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15, the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated, which reduces the data transmission between them and improves systematic integration degree.

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Periodical:

Edited by:

Jianhua Wang, Changfu Zhang, Xiaoli Jin and Jinlong Zou

Pages:

488-496

DOI:

10.4028/www.scientific.net/AMR.411.488

Citation:

Y. Y. Liu et al., "Design of High Speed and Parallel Compression System Used in the Big Area CCD of High Frame Frequency", Advanced Materials Research, Vol. 411, pp. 488-496, 2012

Online since:

November 2011

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$38.00

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