The Implementation of a High Speed Ethernet Traffic Generator Based on FPGA


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High speed Ethernet traffic is important for some system tests which use TCP/IP as the data communication. A software way to do this job brings benefits on robust, but due to the limitation of CPU, it can not give full line speed of Ethernet frame, especially where short frame is needed. An implementation of an embedded high speed network traffic generator which is based on FPGA is introduced. It can be used to generate arbitrary length of PRBS Ethernet frame. Due to the high speed process ability of FPGA, even when the frame length is as short as 64 bytes, the speed is almost the full line speed as the theoretical value, which is 10 times fast than software method.



Advanced Materials Research (Volumes 433-440)

Edited by:

Cai Suo Zhang




J. Wu et al., "The Implementation of a High Speed Ethernet Traffic Generator Based on FPGA", Advanced Materials Research, Vols. 433-440, pp. 7530-7534, 2012

Online since:

January 2012




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