I-V and Surface Topography Study of Nanostructure Porous Silicon Layer Prepared by Electrochemical Etching
This article reports on the electrical properties of porous silicon nanostructures (PSiNs) in term of its surface topography. In this study, the PsiNs samples were prepared by using different current density during the electrochemical etching of p-type silicon wafer. PSiNs has been investigated its electrical properties and resistances for different surface topography of PSiNs via current-voltage (I-V) measurement system (Keithley 2400) while its physical structural properties was investigated by using atomic force microscopy (AFM-XE100).
Mustafizur Rahman, Erry Yulian Triblas Adesta, Mohammad Yeakub Ali, A.N. Mustafizul Karim, Md. Abdul Maleque, Hazleen Anuar, Tasnim Firdaus Mohamed Ariff, NMohammad Iqbal, Noorasikin Samat and Noor Azlina Hassan
F. S. Husairi et al., "I-V and Surface Topography Study of Nanostructure Porous Silicon Layer Prepared by Electrochemical Etching", Advanced Materials Research, Vol. 576, pp. 519-522, 2012