A Variable-Length FFT Processor Base on Mixed-Radix Algorithm for PAPR Reduction in OFDM Systems
An attractive technique of variable-length Fast Fourier transform (FFT) processor is proposed for PAPR reduction in orthogonal frequency division multiplexing (OFDM) systems. Mixed-radix algorithm and single path delay feedback (SDF) pipeline architecture is adopted to obtain low computation complexity and preferable flexibility for its VLSI implementation. The FFT processor can be reconfigured as 512, 1024, 2048, 4096-points, moreover, the only one RAM unit is used for store sine/cosine tables. The chip is mapped to the 0.18 CMOS technology and the core area is 7.896mm2. The experiment results show that the proposed FFT processor is suitable for PAPR reduction in OFDM communication systems.
X. B. Meng et al., "A Variable-Length FFT Processor Base on Mixed-Radix Algorithm for PAPR Reduction in OFDM Systems", Advanced Materials Research, Vols. 588-589, pp. 826-829, 2012