A 10Gb/s Low-Power Front-End Amplifier for Optical Receiver in 0.18μm CMOS Technology


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A Front-End Amplifier for the STM-64(10Gb/s) optical receiver in SDH system has been proposed in TSMC 0.18 μm CMOS technology. The common-gate feedforward configuration with an active inductor is employed in the input stage of transimpedance amplifier to increase the bandwidth. A 3-order interleaving active feedback configuration is employed to expand the bandwidth in the gain stage of transimpedance amplifier and limiting amplifier. Simulation results show that the output swing is 190mV (Vpp) when the input current varies from 20μA to 400μA. The power consumption is only 98.2mW with 1.8V power supply and the chip area is 496μm×480μm.



Advanced Materials Research (Volumes 588-589)

Edited by:

Lawrence Lim




Z. Lei et al., "A 10Gb/s Low-Power Front-End Amplifier for Optical Receiver in 0.18μm CMOS Technology", Advanced Materials Research, Vols. 588-589, pp. 872-875, 2012

Online since:

November 2012




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