Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates


Article Preview

Recently, magnetic tunnel junction (MTJ)-based implication logic gates have been proposed to realize a fundamental Boolean logic operation called material implication (IMP). For given MTJ characteristics, the IMP gate circuit parameters must be optimized to obtain the minimum IMP error probability. In this work we present the optimization method and investigate the effect of MTJ device parameters on the reliability of IMP logic gates. It is shown that the most important MTJ device parameters are the tunnel magnetoresistance (TMR) ratio and the thermal stability factor Δ. The IMP error probability decreases exponentially with increasing TMR and Δ.



Edited by:

Alexei N. Nazarov, Volodymyr S. Lysenko and Denis Flandre






H. Mahmoudi et al., "Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates", Advanced Materials Research, Vol. 854, pp. 89-95, 2014

Online since:

November 2013




[1] A. Whitehead and B. Russell, Principia Mathematica, Cambridge at the University Press, (1910).

[2] E. Shannon, A Symbolic Analysis of Relay and Switching Circuits, Master's thesis, MIT, (1940).

[3] J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, and R.S. Williams, Memristive switches enable stateful logic operations via material implication, Nature 464 (2010) 873–876.

DOI: 10.1038/nature08940

[4] D.B. Strukov, G.S. Snider, D.R. Stewart, and R.S. Williams, The Missing Memristor Found, Nature 453 (2008) 80–83.

DOI: 10.1038/nature06932

[5] N.S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, Leakage current: Moore's law meets the static power, Computer 36 (2003) 68–75.

DOI: 10.1109/mc.2003.1250885

[6] H. Ohno, T. Endoh, T. Hanyu, N. Kasai, and S. Ikeda, Magnetic tunnel junction for nonvolatile CMOS logic, IEDM Tech. Dig. (2010) 9. 4. 1–9. 4. 4.

DOI: 10.1109/iedm.2010.5703329

[7] M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating, Solid-State Circuits Conference Digest of Technical Papers (2013).

DOI: 10.1109/isscc.2013.6487696

[8] H. Mahmoudi, V. Sverdlov, and S. Selberherr, A Robust and Efficient MTJ-based Spintronic IMP Gate for New Logic Circuits and Large-Scale Integration, Proc. of the 17th Int. Conf. on Simulation of Semiconductor Processes and Devices (2012) 225–228.

[9] H. Mahmoudi, T. Windbacher, V. Sverdlov, and S. Selberherr, , Solid-State Electronics 84 (2013) 191–197.

DOI: 10.1016/j.sse.2013.02.017

[10] W. Zhao, L. Torres, Y. Guillemenet, L.V. Cargnini, Y. Lakys, J. -O. Klein, D. Ravelosona, G. Sassatelli, and C. Chappert, Design of MRAM based Logic Circuits and its Applications, ACM Great Lakes Symposium on VLSI (2011) 431–436.

DOI: 10.1145/1973009.1973104

[11] W. Zhao, C. Chappert, V. Javerliac, and J. -P. Nozie, High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits, IEEE Trans. Magn. 45 (2009) 3784–3787.

DOI: 10.1109/tmag.2009.2024325

[12] H. Mahmoudi, T. Windbacher, V. Sverdlov, and S. Selberherr, MRAM-based Logic Array for Large-Scale Non-Volatile Logic-in-Memory Applications, Proc. of the 2013 IEEE/ACM Int. Symp. on Nanoscale Architectures (NANOARCH), (2013) 26–27.

DOI: 10.1109/nanoarch.2013.6623033

[13] H. Mahmoudi, T. Windbacher, V. Sverdlov, and S. Selberherr, Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits, IEEE Trans. Magn., DOI: 10. 1109/TMAG. 2013. 2278683 (2013).

DOI: 10.1109/tmag.2013.2278683

[14] J.C. Slonczewski, Current-Driven Excitation of Magnetic Multilayers, J. of Magn. and Magn. Mater. 159 (1996) L1–L7.

[15] L. Berger, Emission of Spin Waves by a Magnetic Multilayer Traversed by a Current, Phys. Rev. B 54 (1996) 9353–9358.

DOI: 10.1103/physrevb.54.9353

[16] Y. Higo, K. Yamane, K. Ohba, H. Narisawa, K. Bessho, M. Hosomi, and H. Kano, Thermal Activation Effect on Spin Transfer Switching in Magnetic Tunnel Junctions, Appl. Phys. Lett. 87 (2005) 082502.

DOI: 10.1063/1.2011795

[17] M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachinoa, C. Fukumoto, H. Nagao, and H. Kano, A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM, IEDM Tech. Dig. (2005).

DOI: 10.1109/iedm.2005.1609379

[18] Y. Zhang, W. Zhao, Y. Lakys, J.O. Klein, J.V. Kim, D. Ravelosona, and C. Chappert, Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions, IEEE Trans. Electron Devices 59 (2012) 819–826.

DOI: 10.1109/ted.2011.2178416

In order to see related information, you need to Login.