A New Architecture of LCD Driver of Rail-to-Rail Buffer with High Gain Wide Range
A new modified CMOS buffer amplifier with rail-to-rail input and output range is proposed by TSMC 0.35μm 2P4M process at 3.3V supply. The technique adds dummy pairs to sense the common mode range of the input differential pair and adjusts the output current accordingly. The amplifier provides high gain for a wider range of output voltages. Design considerations for reducing the impact of the additional circuitry on the core are provided. The technique described can be adapted for use with traditional fully-differential rail-to-rail amplifiers, which performs 86.9dB ~92dB dc gain, 15 MHz unit-gain bandwidth, high driving ability with high slew rate under a 100pF capacitance and a 3kΩ series resistance loading. The simulation results indicate that the settling times of rising and falling edge are within 3.5μs. It is effective for a high resolution and high speed LCD driver.
Zhengyi Jiang and Chunliang Zhang
S. H. Lin et al., "A New Architecture of LCD Driver of Rail-to-Rail Buffer with High Gain Wide Range", Advanced Materials Research, Vols. 97-101, pp. 3765-3768, 2010