Mapping Based Energy Efficient Counter Design on FPGA

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— In this work, 8-bit counter power optimized counter is designed with help of energy efficient techniques called mapping and simulation activity file in format of Value Change Dump (VCD) file and setting file (*.xpa) to define toggle rate, activity rate and enable rate for the power consumption estimation in order to get energy efficient design. With mapping, there is 33.33%, 34.61%, 36.5%, 36.49%, 36.86%, 36.9% dynamic power reduction in counter when device is operating on 10MHz, 100MHz, 1GHz, 10GHz, 100GHz and 1 THz frequency. This reduction achieved by mapping control signal to control port in place of mapping control signal to LUT (Look Up Table) input. In Resource utilization, when we are mapping the control signal to control port, there is 70.58% less number of LUT and 39.89% less number of IO usage than mapping the control signal to LUT inputs. Spartan-3 FPGA is taken as target device and Xilinx 14.1 ISE is taken as design, synthesis and implementation tools. Verilog HDL(Hardware Description Language) is used to synthesize the counter on FPGA. The power dissipation of the FPGA based energy efficient design is verified using Xilinx XPower tool.

Info:

Periodical:

Advanced Materials Research (Volumes 984-985)

Edited by:

P.M. Diaz, K. Palanikumar and Puli Ravi Kumar

Pages:

1085-1088

DOI:

10.4028/www.scientific.net/AMR.984-985.1085

Citation:

T. Kumar et al., "Mapping Based Energy Efficient Counter Design on FPGA", Advanced Materials Research, Vols. 984-985, pp. 1085-1088, 2014

Online since:

July 2014

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$35.00

* - Corresponding Author

[1] T. Marconi, D. Theodoropoulos, K. Bertels, and G. Gaydadjiev, A novel HDL coding style to reduce power consumption for reconfigurable devices, IEEE International Conference on Field-Programmable Technology (FPT), pp.295-299, (2010).

DOI: 10.1109/fpt.2010.5681480

[2] B. Pandey and M. Pattanaik, Mapping Based Low Power Arithmetic and Logic Unit Design with Efficient HDL Coding, 5th International Conference on Computer Research and Development (ICCRD), Ho Chi Minh City, Vietnam, February 23-24, (2013).

DOI: 10.1115/1.860182_ch40

[3] K. Arshak, E. Jafer, and C. Ibala, Power Testing of an FPGA based System Using Modelsim Code Coverage capability, IEEE Design and Diagnostics of Electronic Circuits and Systems, (2007).

DOI: 10.1109/ddecs.2007.4295273

[4] B. Pandey and M. Pattanaik, Low Power VLSI Circuit Design with Efficient HDL Coding, IEEE International Conference on Communication Systems and Network Technologies (CSNT), Gwalior, India, April 5-8 (2013).

DOI: 10.1109/csnt.2013.149

[5] Pandey and M. Pattanaik, Energy Efficient VLSI Design and Implementation on 28nm FPGA, Lambert Academic Publisher, Germany, 2013, ISBN: 978-3-659-47759-1, EAN: 9783659477591.

[6] S. M. Mohaiminul Islam, Bishwajeet Pandey, Shashank Jaiswal, Md. Mahbub-E-Noor and Shah Md. Tanvir Siddiquee, Simulation of Voltage Scaling Aware Mobile Battery Charge Controller Sensor on FPGA", "Advanced Materials Research, Vol. 893 (2014).

DOI: 10.4028/www.scientific.net/amr.893.798

[7] Bhavani Shankar Chowdhry, Bishwajeet Pandey, Tanesh Kumar, Teerath Das, Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA, Springer Wireless Personal Communications, An International Journal, ISSN: 0929-6212 (print version), ISSN: 1572-834X (electronic version), March (2014).

DOI: 10.1007/s11277-014-1725-z

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