Low Power Devnagari Unicode Checker Design Using CGVS Approach


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In this paper we have introduced a new approach called Clock Gating and Voltage Scaling (CGVS), which is the combination of two existing techniques i.e. Clock gating and Voltage Scaling. Our aim is to design a low power Devnagari Unicode Checker (DUC) using CGVS technique. This design is implemented on Kintex-7 FPGA families, XC7K70T device, -3 speed grade and FBG676 package. From our analysis, it is observed that, with the use of clock gated technique in our target circuit and with the scaling of voltage from 1.0V to 0.1V, we are achieving clock power reduction of 98.98% on 10GHz and 1THz operating frequencies. Under same voltage scaling scheme, there is 6.66%, 10.38%, 10.64% and 10.62% less reduction in IO power, when the target circuit is operating on 1GHz, 10GHz, 100GHz and 1THz operating frequencies.



Advanced Materials Research (Volumes 984-985)

Edited by:

P.M. Diaz, K. Palanikumar and Puli Ravi Kumar






S.M. M. Islam et al., "Low Power Devnagari Unicode Checker Design Using CGVS Approach", Advanced Materials Research, Vols. 984-985, pp. 1282-1285, 2014

Online since:

July 2014




* - Corresponding Author

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