The dependence of transistor characteristics upon the grain-boundary location in polycrystalline Si thin-film transistors was analyzed by means of device simulation. In the linear region, the degradation was similar regardless of where the grain boundary was located. In the saturation region, the degradation was lower when the grain boundary was located in the pinch-off region near to the drain-edge. The degradation was similar when the grain boundary was elsewhere. Although this dependence was similar to that on trap location in monocrystalline Si transistors, the mechanism was different. The dependence in the case of polycrystalline thin-film transistors was attributed to the fact that a coulombic potential barrier, which was caused by the grain boundary, was lowered by the high electric field in the pinch-off region. This was considered to be a form of Poole-Frenkel effect.

Dependence of Polycrystalline Silicon Thin-Film Transistor Characteristics on the Grain-Boundary Location. M.Kimura, S.Inoue, T.Shimoda, T.Eguchi: Journal of Applied Physics, 2001, 89[1], 596-600