The defects created in rapid thermally annealed n-type epilayers, capped with native oxide layers, were investigated by using deep-level transient spectroscopy. The native oxide layers were formed at room temperature by using pulsed anodic oxidation. A hole trap H0, due to interface states or the injection of interstitials, was observed at around the detection limit of deep-level transient spectroscopy in oxidized samples. Rapid thermal annealing introduced 3 additional minority-carrier traps H1 (EV+0.44eV), H2 (EV+0.73eV) and H3 (EV+0.76eV). These hole traps were introduced together with the electron traps, S1 (EC-0.23eV) and S2 (EC-0.45eV), which were observed in the same epilayers following disordering using SiO2 capping layers. Evidence was also found that a hole trap whose deep-level transient spectroscopy peak overlapped with that of EL2 was present in the disordered n-type layers. Capacitance-voltage measurements revealed that impurity-free disordering, using native oxides of GaAs, produced higher free-carrier compensation as compared with SiO2 capping layers.

Electrical Characterization of Impurity-Free Disordering-Induced Defects in n-GaAs using Native Oxide Layers. P.N.K.Deenapanray, H.H.Tan, C.Jagadish: Applied Physics A, 2003, 76[6], 961-4