Stacking layers (SiO2/Si3N4) were used to control the creation of defects in rapid thermally annealed epitaxial GaAs layers. Annealing at 900C introduced 3 electron traps, S1 (Ec - 0.23eV), S2 (Ec - 0.53eV) and S4 (Ec - 0.74eV) into SiO2/n-GaAs. The concentrations of S1 and S4 decreased, by factors of about 28 and about 19 respectively, in Si3N4/SiO2/n-GaAs. The overlap of a hole trap with the S2 peak in Si3N4/SiO2/n-GaAs resulted in an apparent decrease in the concentration of S2 by over 2 orders of magnitude. A lower concentration of defects in the region probed by deep level transient spectroscopy was attributed to the tensile stress which the Si3N4 layer imposed upon the structure during annealing. In addition to S1 and S4, hole traps H1 (Ev + 0.28eV) and H2 (Ev + 0.42eV) were observed in Si3N4/n-GaAs and SiO2/Si3N4/n-GaAs, respectively. The concentration of defects was larger, by about 1.5 times, in the latter structure. It was concluded that SiO2/Si3N4 stacking layers could therefore be used to ensure the spatially selective modification of GaAs-based structures.

Defect Engineering in Annealed n-Type GaAs Epilayers Using SiO2/Si3N4 Stacking Layers. P.N.K.Deenapanray, A.Martin, C.Jagadish: Applied Physics Letters, 2001, 79[16], 2561-3