A 2-dimensional numerical code was developed to model the effect of grain boundaries on the capacitance–voltage (C–V) characteristics of polysilicon diodes. The test structures were lateral polysilicon P+N diodes where the thickness of the film tf deposited by the low-pressure chemical vapour deposition method was 700 or 450nm. The P+ and N doping was performed by ion implantation using, respectively, B in a dose of 2 x 1015/cm2 and P in 2 doses of 1014/cm2 for tf = 700nm and 5 x 1014/cm2 for tf = 450nm. Using scanning electron microscopy, the presence of one grain boundary perpendicular to the junction and localized at 100nm of the interface deposition was observed. A particular investigation was made here of the effect of this grain boundary on the C–V characteristics. The measured C–V characteristics at 100kHz and 1MHz showed that the frequency effect was more important in the case of the weakly-doped film (tf = 700nm). A determination of the series resistance gave the profile doping concentration: abrupt (ND = 5.5 x 1018/cm3) for tf = 700nm and gradual (slope = 5 x 1025/cm4) for tf = 450nm. Using the previous experimental parameters in the 2-dimensional simulation, it was shown that the presence of the perpendicular grain boundary could reduce by up to 25% the capacitance of the diode and decreased considerably the VRP voltage that corresponded to the pinning of the electrostatic potential at the first parallel grain boundary. This effect was more important when the doping was gradual. The fit of the experimental curves gave, in the weak doping case (tf = 700nm), the position of the first parallel grain boundary (LG1 = 37.5nm) and the density of the inter-granular trap states (NT = 3.2 x 1012/cm2). On the other hand, when the doping was relatively strong (tf = 450nm), the fit showed that the C–V characteristic was dominated much more by the doping profile than by the position of the first grain boundary and the density of the inter-granular trap states.

Two-Dimensional Simulation of the Effects of Grain Boundaries on the C–V Characteristics of P+N Polysilicon Diodes. M.Amrani, Z.Benamara, R.Menezla, A.Boudissa, M.Chellali, T.M.Brahim, F.Raoult: Journal of Physics D, 2005, 38[4], 596-603