The electrical activity of defects present in strained Si (SSi) on thin strain-relaxed Si1-xGex buffer layers (SRBs) was evaluated using deep sub-micron CMOS compatible n+/p and p+/n shallow junctions. Strain relaxation was achieved here by introducing a thin C-rich layer in an otherwise uniform Si0.78Ge0.22 epitaxial layer, resulting in an SRB thickness of 248 or 348nm and processing compatible threading dislocation densities in the range of a few 106/cm2. From a combination of electrical measurements (current– and capacitance–voltage; microwave absorption recombination lifetime) and microscopic techniques (electron-beam-induced current; emission microscopy), it was concluded that generation centers associated with the C layer could play an important role. Their electrical activity was shown to depend strongly on the relative position of the C-doped layer with respect to the junction depth. The type of well dopant (implantation) also had a strong impact on the electrical activity of the different defect types present in the epitaxial layers. It was generally found that the 348nm junctions showed a lower reverse current at practical operation temperatures and voltages, while the p+/n diodes exhibited a better performance compared with their n+/p counterparts.

Defect Analysis of Strained Silicon on Thin Strain-Relaxed Buffer Layers for High Mobility Transistors. G.Eneman, E.Simoen, R.Delhougne, E.Gaubas, V.Simons, P.Roussel, P.Verheyen, A.Lauwers, R.Loo, W.Vandervorst, K.De Meyer, C.Claeys: Journal of Physics - Condensed Matter, 2005, 17[22], S2197-210