The majority and minority carrier traps which were introduced into p-type Czochralski-grown wafers during 2-step low-high temperature annealing were investigated by using deep-level transient spectroscopy. It was shown that plate-like silicon oxide precipitate surfaces, and punched-out dislocations, introduced majority carrier traps having deep energy levels (Ev + 0.43eV and Ev + 0.26eV, respectively) in the band gap; with concentrations that were proportional to the corresponding defect density. The minority carrier traps were positioned at Ec - 0.42eV and Ec - 0.22eV. The majority carrier trap density on the surface of plate-like precipitates was estimated to be 3 x 109/cm2 and the linear trap density for punched-out dislocations was 4 x 104/cm.

Electrical Activity of Defects Induced by Oxygen Precipitation in Czochralski-Grown Silicon Wafers T.Mchedlidze, K.Matsumoto, E.Asano: Japanese Journal of Applied Physics - 1, 1999, 38[6A], 3426-32