A systematic study was made of the conduction process in polycrystalline-Si thin film transistors using carrier flow parallel and perpendicular to sub-grain-boundaries in sequentially laterally solidified material. The objective here was to obtain an unambiguous characterization of grain boundary behavior. By studying orthogonal thin film transistors in this anisotropic material, it was possible to distinguish grain boundary carrier trapping from intragrain trapping. In conventional poly-Si, the material was isotropic over distances greater than the grain size of ~300nm, and there was no direct and clear-cut way of distinguishing between intragrain and intergrain trapping centres. In the experimental samples, the thermal activation energy of the channel current was measured in the two orthogonal directions, and the difference in activation energy was related to carrier flow over perpendicular sub-grain boundaries. The detailed interpretation of the experimental results was facilitated by 2-dimensional numerical simulations, demonstrating that a planar barrier grain boundary, which simply resulted in a potential barrier within the channel, was fundamentally incompatible with the experimental drain current activation energy data. It was only possible to obtain a satisfactory representation of all the experimental data by using a finite width grain boundary, in which carrier flow was controlled by transport across the resistive grain boundary region, rather than by emission over a barrier. This representation of the sub-grain boundary permitted the essential combination of reduced field effect mobility, for orthogonal carrier flow, and a drain current activation energy, which was close to zero.

Grain Boundary Evaluation in Sequentially Laterally Solidified Polycrystalline-Silicon Devices. A.Valletta, A.Bonfiglietti, M.Rapisarda, L.Mariucci, G.Fortunato, S.D.Brotherton: Journal of Applied Physics, 2007, 101[9], 094502