Because of their very large integration capabilities and continuous scaling, the CMOS devices were the basic element in the current-integrated circuits. Their scaling up to sub-micrometric scale presented advantages such as a diminution of power consumption, faster devices and a larger level of integration. But other limitations began to be important at these dimensions: anomalous effects like hot electrons, leakage currents and punch-through, and others, appeared. These effects could be reduced if, at the source/drain region, shallow junctions were obtained with junction depths, xj, less than 200nm. In order to achieve this goal, new junction fabrication methods, which included pre-amorphization were required. Other alternative techniques, which did not require ion implantation in order to prevent surface crystal damage and as a consequence the inhibition of B interstitial clusters and {311} defects, which were the trigger for transient enhanced diffusion were used. It was shown here that rapid thermal processing permitted the fabrication of very shallow junctions, with an xj value less than 300nm, by using high energies and high doses of B/BF2 ion implantation. In this way, slow dissolution of dislocation loops, present at the end-of-range of implanted B, permitted this process. The junctions obtained were compared with those prepared by using the spin-on doping technique. The diffusion profiles obtained using both processes, and their electrical properties, were measured and compared for their application as S–D regions.

Very Shallow Boron Junctions in Si by Implantation and SOD Diffusion Obtained by RTP. J.P.Castillo, A.T.Jácome, O.Malik, N.T.López: Microelectronics Journal, 2008, 39[3-4], 678-81