The cause of warpage of 3C-SiC wafers was analyzed. From ex situ curvature measurements and stress calculations, it was deduced that large compressive intrinsic stress was generated during high-temperature growth (1623K) in both parallel and perpendicular directions. To investigate the intrinsic stress distribution along the 3C-SiC film thickness direction, reactive-ion etching (RIE) of 3C-SiC films was carried out and the dependence of the SiC/Si system curvature on the remaining 3C-SiC thickness was determined. The intrinsic stress component perpendicular to the ridge of undulation exhibited a non-uniform distribution along the film thickness. Below the 50 µm thickness region, the distribution presented large variation. The obtained intrinsic stress distribution was very similar to the stacking fault distribution, which showed high density near the SiC/Si interface and rapidly decreased within 50 µm apart from the interface. The simulation by finite element method has clearly explained that the anisotropic warpage of SiC wafer was led by the intrinsic stress distribution in a quantitative manner. Microstructure changes induced by the stacking fault reduction process (stacking fault collision) would be the cause of the intrinsic stress variation.

Saddle-Shape Warpage of Thick 3C-SiC Wafer: Effect of Nonuniform Intrinsic Stress and Stacking Faults. Y.Sun, S.Izumi, S.Sakai, K.Yagi, H.Nagasawa: Physica Status Solidi B, 2012, 249[3], 555–9