The comprehensive investigation on the effect of dislocation edge stress for Si n-type metal-oxide-semiconductor field-effect transistors was presented here by the experimental measurement and proposed simulation model. The accurate stress measurement in Si OD region with and without dislocation edge stress treatment was extracted by atomic force microscope-Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment was observed successfully and had its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment were the more stress relaxation of the STI intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM-Raman spectra experimentally, the simulated stress from proposed finite element method, and its corresponding electrical characteristics agreed well with each other here. After the comprehensive understanding and calibrated model for the dislocation edge stress, the relationship between channel stress and dislocation edge shapes, including the angle and length of dislocation lines was simulated and investigated clearly. It could be found that longer dislocation line and smaller dislocation angle could relax the intrinsic STI compressive stress more and should have the better electron carrier mobility and device performance for N-MOSFETs.

The Systematic Study and Simulation Modeling on Nano-Level Dislocation Edge Stress Effects. M.H.Liao, C.H.Chen, L.C.Chang, C.Yang: Journal of Applied Physics, 2012, 111[8], 084510