SiGe-on-insulator substrates with different Ge fractions were fabricated using Ge condensation technique. High acceptor concentration (NA) in SiGe-on-insulator layer and interface-trap density, Dit, at SiGe-on-insulator/buried oxide interface were found by using back-gate metal–oxide–semiconductor field-effect transistor method. For the reduction of high NA and Dit, Al deposition and the subsequent post-deposition annealing were carried out. As a comparison, forming-gas annealing was also performed in H2 ambient. It was found that both post-deposition annealing and forming-gas annealing effectively reduced NA and Dit for low-Ge% SiGe-on-insulator. However, with an increase in Ge%, forming-gas annealing became less effective while post-deposition annealing was very effective for the reduction of NA and Dit.
Defect Control by Al Deposition and the Subsequent Post-Annealing for SiGe-on-Insulator Substrates with Different Ge Fractions. H.Yang, D.Wang, H.Nakashima, K.Hirayama, S.Kojima, S.Ikeura: Thin Solid Films, 2010, 518, 2342-5