Defect and Diffusion Forum

Preface

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452

The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and Their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Jimmy Thörnberg, Björn Magnusson
Results from optical defect inspections, and X-ray topography, on wafers from entire 4H-SiC ingots provide a clear visualization on the positional dependance of bulk inclusions in ingots with respect to growth stages, looking to both density and size. It is also clear while studying the superpositioning of Laue–Bragg interference densities that the different categories of said defectivity generate new crystallographic defects, dislocations. These in turn lead to significant reductions in usability of wafers, and the lack of tracing such defects, cause an increased difficulty to predict the final device yield, as is displayed by growing epitaxial layers on materials heavily affected by bulk inclusions.

Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Wei Ning Qian, Fei Hong Huang, Ji Nan Li, Gan Feng, Yong Qiang Sun, Jian Hui Zhao, Jun Yong Kang
Surface pits in silicon carbide (SiC) epitaxial layers have a significant impact on various types of SiC devices, potentially causing electric field concentration and degrading device performance. The formation mechanism of surface pits remains unclear. In this work, the mechanism was investigated through the molten KOH etching experiments, and we confirmed that surface pits originate from dislocation defects in the substrate, particularly TSDs. The dislocations negatively impacted the step-flow growth of epitaxy, leading to pit formation. Further investigations into the effects of growth temperature, C/Si ratio, and epitaxial-layer thickness on pit formation revealed that low temperatures and silicon-rich conditions could effectively suppress pit formation. Both the density and size of surface pits increased significantly with the increase in epitaxial layer thickness. Therefore, this work proposes a model for the formation mechanism of surface pits, where the competition between step-flow growth and spiral growth is a key factor in controlling the size of surface pits.

Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Christian Wißgott, Birgit Kallinger, Mathias Rommel
The quality of the epitaxial layer plays an important role in the performance of modern power electronic devices. Minority carrier lifetime is known to be sensitive to defects like dislocations, stacking faults, and points defects. Therefore, in this work lifetime measurements by microwave detected photoconductivity decay are used to evaluate the quality of the epitaxial layer on various 4H-SiC substrates from different vendors. The stability of the measurement technique is shown by a daily release measurement. This allows for a reliable analysis of almost 300 typical 1,200 V epilayer stacks. It has been shown that the effective lifetime of these samples can be separated into two different ranges. The lifetime values of about 120 ns fit to theoretical calculations. The cause for the increased lifetime of about 250 ns in the second range has yet to be determined in further research. Furthermore, the lifetime maps were used to locate defects in the surface near regions.

DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Lan Luo, Yu Zhong, Xiao Shuang Yang, Quan Xin Zhao, Peng Cui, Ying Xin Cui, Ming Sheng Xu, Xian Gang Xu, Ji Sheng Han
This paper investigates the effect of DLTS measurement parameters on characterizing deep level defects in 4H-SiC Schottky barrier diode (SBD). By adjusting parameters such as the time window (tW), pulse time (tP), reverse voltage (UR), and pulse voltage (UP), the underlying mechanisms influencing defect peak positions, signal amplitudes, and peak broadening are analyzed. Experimental results reveal three deep level defects identified in 4H-SiC SBD: majority carrier traps T1 (EC - 0.66 eV) and T2 (EC - 1.0 eV), along with minority carrier trap T3 (EV + 1.1 eV). Parameter settings not only influence defect characterization sensitivity and concentration calculations but also reveal the dynamics of carrier capture and emission. Through the thorough analysis of the DLTS signal and behavior under different DLTS measurement conditions, the electronic properties and concentration profiles of deep level defects in 4H-SiC epitaxial layers are determined.

Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Zhen Xing Fu, Xiang Long Yang, Xiu Fang Chen, Xue Jian Xie, Li Sun, Hong Yu Shao, Wen Hao Han, Hong Xi Wang, Guo Jian Yu, Xian Gang Xu
8-inch 4H-SiC single crystals were grown under different temperature fields and nitrogen doping conditions by physical vapor transport method. The distributions of basal plane dislocation (BPD) in 4H-SiC single crystals under different growth conditions were studied by molten KOH etching and X-ray Topography (XRT). The results indicate that the BPDs in the crystals grown under convex temperature field are distributed at the edge. In comparison, the BPD distributions in crystals grown under a concave temperature field are relatively closer to the center. Furthermore, the BPDs distributions in nitrogen-doped crystals exhibit quadratic symmetry caused by prismatic slip. In contrast, no prismatic slip-induced slip bands were observed in the undoped crystals, and the BPD distributions in the undoped crystals are consistent with the shear stress distribution caused by basal plane slip.

DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Rosine Coq Germanicus, Gabriel Ferro
Local electrical properties of a 4H-Silicon Carbide SiC(0001) 4°off macrostepped surface, obtained after liquid Si melting in a SiC/Si/SiC sandwich configuration, are investigated by Atomic Force Microscopy (AFM) in both DC and RF modes. On the same sample, macrosteps that are wide enough for allowing spatial resolution of the signal from terraces and step risers, but also some unreacted areas with standard flat surface (without macrosteps) are characterized. Scanning Spreading Resistance (SSRM, DC mode) reveals homogeneous conductivity on the wide terraces of the 4H-SiC(0001) macrosteps. On unreacted areas, which contain many step risers, the resistance is found higher than on the wide terrasses but it is also noisier. In addition, the AFM-RF scanning Microwave Impedance Microscopy (sMIM) mapping confirms the previous results by revealing lower conductivity on the unreacted areas than on the terraces of the macrosteps. Based on these results, some points defects located at the step risers which contribute negatively to the electrical properties of 4H-SiC(0001) surface are identified and electrically characterized.

Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Nicolo Piluso, Cristiano Calabretta, Fabiana Vento, Ruggero Anzalone, Chiara Nania, Domenica Raciti, Antonio Rossitto, Alice Lombardo, Mario Coppola, Annalisa Cannizzaro, Andrea Severino, Giuseppe Arena, Matteo M. Salamone, Federico Giuffrida, Luca Barbisan, Parikshit Sharma, Jeff Per, Manoj Kumar Dayyala, Paola Parisi
A new design approach on 4H-SiC material is ongoing to improve the electrical performance of devices. As seen in silicon devices, multi-epitaxial growth enhances performance by reducing on-resistance (Ron). However, devices built on SiC face several challenges due to the very low dopant diffusion (e.g. phosphorus and aluminum) and defect evolution during the epitaxial growth. Monitoring defects like prismatic faults, stacking faults, partial dislocations, and micropipes, especially after regrowth, is essential to assess their impact on device performance. Defects with high killer ratio must be closely tracked to understand evolution thereof. In this work, we will show a method for early-stage process characterization and defect root-cause identification through sensitive inspections, effective reviews, and accurate defect classification to detect critical defects in 4H-SiC material when more than one epitaxial step is considered.

Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Zimo Yuan, Alex Metreveli, Lasse Vines, Orazio Samperi, Misagh Ghezellou, Jawad Ul-Hassan, Anders Hallén
In this paper, the temperature dependence of charge carrier lifetimes in n-type 4H-SiC epitaxial layers is studied in a temperature range of 300-500 K. It is assumed that shallow (B) and deep (D) boron-related defects are the dominating lifetime killers in as-grown epitaxial layers. The thermodynamic behavior of these two types of defects is obtained from DLTS measurements, and implemented in the Shockley-Read-Hall (SRH) model to calculate lifetimes, using Gibbs free energies to describe the accurate temperature dependence for capture and emission processes of the defects. Calculation results show that the lifetimes controlled by shallow boron defects increase with increasing temperature, while D-defects give the opposite temperature dependence. The theoretical results are also compared to measured data from 10 kV 4H-SiC PiN-structures, showing that the temperature dependence of the effective lifetime can be changed by proton implantations, which gives rise to additional Z1/2 defects that have similar temperature effects on lifetimes as D-related defects.

Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Li Sun, Xue Jian Xie, Xiu Fang Chen, Xiang Long Yang, Yan Peng, Xiao Bo Hu, Xian Gang Xu
Micropipe defects in silicon carbide (SiC) materials significantly degrade the performance of SiC materials and their applications in semiconductor devices. In this study, systematic methods were utilized to characterize different micropipes in 4H-SiC. X-ray topography was employed to investigate the morphology of micropipe defects in SiC substrates and quantify their associated lattice distortion fields. Meanwhile, white light interferometry mode microscopy and inner stain were utilized to thoroughly characterize their properties. It was found that micropipes were accompanied with different size and distortion areas in SiC substrate. This work will be served as a refined characterization of micropipes and give guidance for device application for SiC substrate.

High Quality P-Type 4H-SiC Growth by PVT Method

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Shan Shan Hu, Hao Chi Wang, Ze Yu Chen, Kai Xuan Zhang, Yu Zhuo Li, Jian Pei Zhang, Balaji Raghothamachar, Michael Dudley, Douglas Dukes, Victor Torres
The fabrication of n-channel IGBTs is constrained by the low conductivity as well as poor quality of the p-type SiC substrate. This paper reports 6-inch high quality p-type 4H-SiC wafers achieved by PVT method. The wafers were examined by synchrotron X-ray topography indicating average defect densities are on par or better than commercial 6-inch n-type wafers. Large areas of the wafer, especially the middle region of the wafer is characterized by very low density of BPDs. The extent of prismatic slip due to radial thermal gradients is also vastly reduced compared to typical n-type wafers.

Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Hitesh Jayaprakash, Manuel Belanche, Constantin Csato, Florian Krippendorf, Ulrike Grossner, Michael Rueb
The extensive study of point defects in 4H-SiC over the past two decades has led to a comprehensive understanding of their influence on device performance. Specifically, the dominant defects Z1/2 and EH6/7 have been well-quantified and are now formally assigned to specific states of the carbon vacancy. Building upon this foundational knowledge, our study investigates the defect landscape created by the novel process of Energy-Filtered Ion Implantation (EFII). Using DLTS and MCTS measurements conducted within the temperature range of 50−650 K, we analyzed the trap levels created by 19 MeV Nitrogen implantation in as-grown 4H-SiC epitaxial wafer. The majority carrier (electrons) trap with DLTS measurements reveal the presence of prominent peaks associated with carbon complexes, labeled as ON0a (Ec - 0.586 eV) and ON0b / Z1/2 at (Ec - 0.681 eV), along with smaller peaks in the shallow region and a broader peak identified as EH6/7 at (Ec - 1.53 eV) as the deepest peak. Notably, the close proximity of the ON0b peak to the well-known Z1/2 peak poses a significant challenge, preventing the definitive assignment of a defect structure to the known carbon complexes. On the contrary, minority carrier (holes) trap detection with MCTS reveal B-center at (EV + 0.24 eV) and (EV + 0.33 eV) and a negligible shallow peak at (EV + 0.22 eV) assigned as X center. There was no indication of D-center formation in the EFII implanted samples.

Observation and Analysis of the “Galaxy” Defect in 4H-SiC through X-Ray Synchrotron Topography

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Kai Xuan Zhang, Ze Yu Chen, Shan Shan Hu, Jian Pei Zhang, Yu Zhuo Li, Dong Lin Wu, Hao Chi Wang, Balaji Raghothamachar, Michael Dudley, Andrey Soukhojak
Silicon carbide (SiC) is valued for high-power and high-frequency devices, but its performance is limited by crystalline defects. We report a newly observed defect arrangement, termed the “galaxy” defect, in wafers from a PVT-grown 6-inch 4° off-axis boule. Optical microscopy revealed dense clusters of micron-sized inclusions, while synchrotron X-ray topography (XRT) showed associated dislocation networks. Transmission synchrotron XRT indicated threading dislocation clusters, and grazing images revealed high densities of basal plane dislocations, deflected Frank partials, and threading-edge-dislocation low-angle grain boundaries (TED-LAGBs). The defect evolved as growth progressed, producing increasingly complex dislocation structures. Based on the observation, we proposed a mechanism for the evolution of the defect involving the generation, evolution, and interaction between the inclusions and dislocations.

Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Yu Zhuo Li, Jian Pei Zhang, Ze Yu Chen, Hao Chi Wang, Kai Xuan Zhang, Shan Shan Hu, Balaji Raghothamachar, Albert A. Burk Jr, Kanwar Singh, Muhammad Ali Johar, Nadeemullah A. Mahadik, Robert E. Stahlbush, Michael Dudley
Silicon carbide is a leading wide-bandgap semiconductor for high-voltage power electronics. For 6.5–10 kV operation, thick epitaxial layers (≥60 µm) are required to sustain depletion width and maintain uniform electric fields, placing a premium on low extended-defect densities in both substrate and epilayer. Thick epitaxial 4H-SiC layers of 60 µm and 110 µm were grown on 6-inch substrates in a multi-wafer warm-wall reactor and evaluated by synchrotron X-ray topography in grazing-incidence (22-4 16) and transmission (11-20) geometries. Transmission imaging showed substrate dislocation content near the lower bound typically reported for 6-inch wafers. Notably, grazing-incidence topography (penetration depth >40 µm) revealed no basal-plane dislocations propagating into the epilayers, consistent with efficient dislocation conversion at the substrate–epilayer interface. The 3C-SiC inclusion density was ~30 per 6-inch wafer for 60 µm epilayers and ~60 per wafer for 110 µm epilayers; the average micropipes density varies from 0 to 5 for both 60 and 110 um epiwafers. Threading dislocation densities—screw, edge, and mixed—were on the order of 1.0–2.0 × 10³ cm⁻². These results establish thick 4H-SiC epilayers with suppressed basal-plane propagation and substantially reduced extended-defect content, providing a strong basis for reliable 6.5–10 kV device fabrication.

Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Dong Lee, Kirby Schmidt, Muhammad Ali Johar, Shanthi Subramanian, Albert Burk, Andy Souzis
The performance and reliability of silicon carbide (SiC) devices are critically dependent on the quality of epitaxial layers which in turn are influenced by substrate properties. The accurate classification of epitaxial defects coming from substrate crystal defects and surface defects is critical since these can adversely affect device performance. In this paper, two new methods of defect characterization in substrates and epitaxial layers are presented utilizing photoluminescence (PL) spectrum and carrier lifetime. These methods can be used to study the evolution of defects from substrates to epi and to better predict Epi yields.

Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Mon, 18 May 2026 00:00:00 +0200

Publication date: 18 May 2026
Source: Defect and Diffusion Forum Vol. 452
Author(s): Cristiano Calabretta, Nicolo Piluso, Ruggero Anzalone, Enzo Fontana, Giovanni Maira, Gabriele Bellocchi, Mario S. Alessandrino, Fabiana Vento, Chiara Nania, Salvatore Adamo, Sonia Zappalà, Giuseppe D'Arrigo, Elisa Vitanza, Nella Bentivegna, Alfio Russo, Giuseppe Arena, Andrea Severino
The fabrication of high-quality 4H-SiC epitaxial layers for power semiconductor devices involves complex processes including bulk crystal growth, wafer slicing, polishing, and chemical vapor deposition (CVD) epitaxy with precise step-flow control on slightly off-cut Si-face substrates. Despite advances, intrinsic crystallographic defects such as threading dislocations, basal plane dislocations, and stacking faults remain significant challenges, propagating into epitaxial layers and degrading device performance and reliability. This study examines defect types and their impact on 4H-SiC wafers, emphasizing the transition from 150 mm to 200 mm substrates, which introduces increased defect densities and polytype inclusions. Comprehensive defect characterization using advanced microscopy, molten KOH etching, and electrical wafer sorting reveals strong correlations between physical defects—such as micropipes, carrot-like stacking faults, and triangular 3C-SiC inclusions—and device failures, particularly under reliability stress tests like High Temperature Reverse Bias (HTRB). The findings highlight the critical role of substrate quality, epitaxial growth conditions, and defect mapping in improving yield and device robustness. This work underscores the necessity of integrating multi-scale defect inspection and targeted reliability assessments to optimize 4H-SiC power device manufacturing and performance.