Journal of Nano Research Vol. 36

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Authors: Narendra G. Sarda, Hiroshi Fujigaki, Yuma Ogita, Andrew Chan, Kei-Ichiro Murai, Geoffrey I.N. Waterhouse, Toshihiro Moriga
Abstract: (Ba1-(x+y)SrxEuy)2Si6O12N2 oxynitride phosphors were successfully synthesized by the solid-state reaction method at 1200°C under a H2(5%) + N2(95%) atmosphere. The Sr2+ content (x) was varied in the range 0-0.6 and the Eu2+ content varied in the range 0.05-0.25, with the Si/(Ba+Sr+Eu) ratio fixed at 3. Results showed that the emission characteristics of (Ba1-(x+y)SrxEuy)2Si6O12N2 phosphors under UV or blue-light excitation was strongly dependent on the chemical composition. The phosphor (Ba0.95Eu0.05) Si6O12N2 showed an intense green emission peak at 520 nm, whilst the phosphor (Ba0.45Sr0.5Eu0.05)Si6O12N2 had a weaker emission maximum at 548 nm. Ba2+ substitution with Sr2+ decreased the lattice volume of the (Ba1-(x+y)SrxEuy)2Si6O12N2 phosphors and was responsible for the red-shift in the emission peak. Optimization of the Eu2+ concentration at a fixed Sr2+ content of 0.2 identified the phosphor (Ba0.65Sr0.2Eu0.15)2Si6O12N2 as a potential alternative to YAG:Ce yellow phosphors for white LED applications.
Authors: Neetu Prasad, Anita Kumari, P.K. Bhatnagar, P.C. Mathur
Abstract: In the present work, we report fabrication and electrical characterization of a back gated graphene field effect transistor (GFET). We have focused our study on the interfacial effect (graphene/SiO2) on the performance of the device. Hysteresis was observed in the drain conductance when measured with respect to dual gate sweep voltage, which increases with increasing sweeping voltage range. The conductance was observed to increase with increase in temperature but there was no reduction in the hysteresis. This proved that temperature annealing could improve the channel conductivity but not the interfacial effects. Further, a metal oxide semiconductor (MOS) device was fabricated with SLG inserted in between the metal and oxide layer and its capacitance-voltage (C-V) characteristics were studied. A small series capacitance (2.1 nF) was observed to be existing in series with the oxide capacitance (4.5 nF) which was attributed to the trap states at the interface of graphene and SiO layer. Also, the flat band voltage was not affected by the incorporation of graphene layer in the MOS device indicating no change in the work function of the metal gate (Cr/Au). This is an advantageous situation where graphene does not alter its work function also being impermeable, restricts the diffusion of metal particles through the SiO2.
Authors: Debarati Dey, Pradipta Roy, Tamoghna Purkayastha, Debashis De
Abstract: Thanks to the world of nanotechnology; it is possible to build molecular nanodevices. In this paper, GaAs single nanowire molecular p-i-n diode is designed and its electronic transmission properties, Local Device Density of States, Highest Occupied Molecular Orbital-Lowest Unoccupied Molecular Orbital plot and Negative Differential Resistance property are investigated from the atomic perspective using first principle Density Functional Theory-Non Equilibrium Green Function approach. This molecular structure is built and simulated in Virtual nanoLab atmosphere. The Negative Differential Resistance of the device is revealed through the current-voltage characteristics of the nanowire. The band-to-band tunneling current is observed for this p-i-n junction nanodiode. Thermal coefficient, Peltier co-efficient, and Seebeck coefficients at different gate bias are obtained. This nanowire GaAs molecular diode is attractive for the next generation low power nanodevice design. Electrical doping effect has been introduced in the wire without adding unambiguous dopants to the molecular wire.
Authors: Upasana, Rakhi Narang, Manoj Saxena, Mridula Gupta
Abstract: The paper presents an in-depth study of device physics and development of a generalized model (Accumulation-Depletion-Inversion Mode) for Hetero-Dielectric based TFET Architecture. A comparative study among single dielectric (high-k and low-k dielectric materials) and dual-dielectric (Hetero-Dielectric) based p-i-n and p-n-i-n TFET architectures has also been made. The model includes the impact of dielectric length variation and mobile charge carriers which has been validated through the Vgs and Vds dependent effective potential at the channel center of the device. Several physics based parameters such as surface potential, energy band profile, total electric field and drain current (both Ids-Vds and Ids-Vds) have also been investigated. Further, the model has been extended to optimize the Hetero-Dielectric p-n-i-n TFET by tuning the gate work function and length of the dielectric material. While optimization various static parameters such as Subthreshold Swing (SS), threshold voltage, Ion/Ioff ratio and dynamic performance parameters (parasitic capacitances) i.e. total gate capacitance (Cgg), gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) have been investigated. The efficacy of the model has been validated through simulation results obtained using ATLAS device simulator.
Authors: Pankaj M. Koinkar, Sandip S. Patil, Toshihiro Moriga, Mahendra A. More
Abstract: Electrochemical synthesis of Polypyrrole (PPy) thin films on Sn substrates has been carried out under cyclic voltammetry (CV) mode. The structural, morphological and chemical properties of the as-synthesized PPy films were investigated using various characterization techniques like SEM, UV-Visible and FTIR. Furthermore, field emission (FE) behaviour of the PPy thin film emitter were carried out at base pressure of ~ 1×10-8 mbar and found to be interesting. The threshold field, required to draw emission current density of 1 μA/cm2, is observed to be 0.90 V/μm and very high emission current density of 12.87 mA/cm2 has been drawn at applied field of ~ 2.8 V/μm. The emission current stability investigated at preset values of 1, 10 and 100 μA/cm2 is observed to be fairly good over duration of more than three hours. The simplicity of the synthesis route coupled with the capability to deliver very high emission current density at relatively lower applied field make the PPy thin field emitter as a potential candidate for practical applications in field emission based devices
Authors: Vandana Kumari, Manoj Saxena, Mridula Gupta
Abstract: This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.
Authors: Sanjeet Kumar Sinha, Saurabh Chaudhury
Abstract: In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.

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