3D Simulation Investigating ZnO NWFET Characteristics

3D Simulation was carried out and compared with fabricated ZnO NWFET. The device had the following electrical output characteristics: mobility value of 10.0 cm2/Vs at a drain voltage of 1.0 V, threshold voltage of 24 V, and subthreshold slope (SS) of 1500 mV/decade. The simulation showed that the device output results are influenced by two main issues: (i) contact resistance (Rcon ≈ 11.3 MΩ) and (ii) interface state trapped charge number density (QIT = 3.79 x 1015 cm-2). The QIT was derived from the Gaussian distribution that depends on two parameters added together. These parameters are: an acceptor-like exponential band tail function gGA(E) and an acceptor-like Gaussian deep state function gTA(E). By de-embedding the contact resistance, the simulation is able to improve the device by producing excellent field effect mobility of 126.9 cm2/Vs.


Introduction
Modelling and simulation of semiconductor devices provides an important method of analysis; easily verified, communicated and understood [1][2][3][4][5]. Before any fabrication can be carried out, there is a need to simulate so as to improve understanding, save costs and time. More importantly, it can also predict unknown future behaviours of devices and determine ways of reaching such lofty ideals. Over the years, researchers have developed the software into 2D and 3D. 2D is faster and works best for micro-meter devices, whereas, 3D is slower but it is a requirement for nano-meter devices.
3D simulation is used to characterise earlier work at the University of Southampton by S. M. Sultan, et al., [1] on ZnO NWFET and finds ways of improving it. The device had a p-typed boron doped silicon substrate, an oxide thickness of 100 nm and nanowire dimensions of length 10 µm, width 40 nm, and thickness 36 nm. The electrical characteristics included a field effect mobility of 10.0 cm 2 /Vs at a drain voltage of 1V, a threshold voltage of 24 V, a subthreshold slope (SS) of 1500 mV/decade and an on/off ratio current ratio of 10 6 . By analysing the characteristics of the device, it is clear the device has room for improvement. The field effect mobility is low compared with ZnO TFTs that have mobility around 110 cm 2 /Vs [2] , while state of the art top-down ZnO nanowire transistors have reported mobility of 80 cm 2 /Vs [3]. The threshold voltage is high and needs to be reduced to a value close to 0.5 V. A value close to 0.5 V is desired so as to reduce power consumption. The subthreshold slope is also poor and need to be improved.
Little work on 2D simulation has been reported on ZnO TFTs [4][5][6][7][8] and even less has been reported on 3D simulation of ZnO NWFETs. The work reported is therefore expected to provide new insights into the performance of ZnO NWFETs.

Simulation Procedure
Two Silvaco products were used: Devedit [9] and Atlas [10]. Fig. 1 shows the 3D device structure that was developed using Devedit, whereas electrical characteristics and bias conditions were simulated through Atlas. The structure is assumed to have a single crystal ZnO channel with parameters as stated in Table 1. The research investigation uses Devedit over Athena software because Devedit has a more advanced mesh definition which allows for greater accurate and precise output results. Devedit also allows for direct 3D interfacing with Atlas whereas it is impossible with the Athena software. Atlas numerical methods used for calculating device output results are: newton and direct. Block cannot be used in 3D simulation and gummel is very slow to utilize. Therefore the numerical methods used throughout the simulation are newton and direct. Under ATLAS, the physical model used is the Boltzmann model which is sufficient in this case because the other models are for specific situations such as heavily doped regions, low temperatures that tend to freeze the carriers, and for bipolar transistors. No mobility model was used therefore, Atlas used the default values which are entirely isotropic in nature and there is no directional component. ZnO is a new material and ATLAS software does not cater for ZnO mobility models. For recombination models, the Shockley-Read-hall (SRH) model was utilized as it is the most general model for simulating new materials [10]. Impact ionization models include: Silberrherr's model, Grant's model, Crowell-Sze model, Toyabe model, and Concannon model. All these models are used for breakdown voltage. The breakdown voltage will not be simulated hence these models are not required [10]. Si Substrate thickness 7.0x10 -5 7.0x10 -5 cm 3D simulation is slower and more complex than 2D simulation [11][12][13][14][15][16][17][18]. Its main advantage over 2D simulation is that it allows for a more precise and accurate estimation of the experimental device. The curved shapes that are inherent within device fabrication were not simulated but rectangular shapes were assumed instead for simplicity. This infers that the edges are not accurately characterized. Also surface roughness was not simulated. Surface roughness can be simulated by introducing zig-zag shapes on the surface of the channel. The problem is that experimentally measured roughness is between 1.5 nm to 6.0 nm which is too small for efficient convergence. The density of donor-like states in the tail distribution at the valence band edge, NTD  10 The total density of acceptor-like states in a Gaussian distribution, NGA  11 The total density of donor-like states in a Gaussian distribution, NGD Defects are very important in modelling the performance of ZnO nanowire FETs. Two types of charge defects were investigated which are surface charge and interface state trapped charge (QIT). Surface charge was simulated by including it in the oxide fixed charge parameter (Qf). Interface state trapped charge was modelled using Equation 1 and shows that the density of defect states (DoS = g(E) which defines the trapped charge) depends on two functions: an acceptor-like exponential band tail function gGA(E) and an acceptor-like Gaussian deep state function gTA(E) [11,13,14] N-type ZnO semiconductor contains defect states mainly due to acceptor-like trapped charge. Equations 2 & 3 describe the gGA(E) and gTA(E) functions, where: a. NGA is the density at peak energy, b. EGA is the peak energy, c. WGA is the Gaussian decay energy for the Gaussian distribution gGA(E) d. NTA is the conduction band edge intercept density, e. WTA is the Gaussian decay energy for the Gaussian distribution gTA(E) Interface state trapped charge (QIT) was therefore modelled by fitting the parameters within the above set of equations to the measured ZnO nanowire FET characteristics. Starting with parameters from literature on ZnO FETs [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], all parameters were varied as shown in Table 2 but still kept within the literature values.
After modelling a basic n-type ZnO nanowire field effect transistor, the simulation was then compared with experimental results [1]. The values are presented on Table 3. The top-down fabrication process utilized remote-plasma atomic layer deposition (RP-ALD) at 190 °C and anisotropic inductively coupled plasma (ICP) etching at an RF power of 100 W and pressure of 15 mtorr.  (2) to get the true experimental representation. Table 1 shows the physical parameters that were used to define the ZnO NWFET whereas Table  2 shows the parameters used to characterize the defects. All simulation parameters were obtained wherever possible from measurements on an experimental device reported in the literature [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The donor concentration for the nanowire was measured experimentally to be between 2.0 x 10 16 and 3.0 x 10 16 cm -3 . The silicon substrate doping is derived from a p-type resistivity between 1 and 30 Ω.cm. Fig. 1 shows a Devedit 3D structure with two ZnO nanowires that act as the active channel modelled through parameters stated in Table 2. It is composed of bottom and side oxide layers which are 10 µm and 100 nm respectively. It possesses source-drain pads that help reduce the contact resistance by providing a large surface area for the metal electrodes to connect with the nanowires. These metal electrodes are deposited on top of the pads. Two nanowires are very slow to simulate due to mesh constraints, therefore one nanowire is simulated as depicted in Fig. 2. Fig. 3 shows the initial 3D simulated subthreshold IDSVGS characteristic for a ZnO nanowire transistor using default parameters derived from literature [10][11][12][13]. These parameters are summarised in Table 2 where they are compared with the final ones used. At this point, no defects were introduced at the oxide/channel interface. Default parameters give a high current and a steep sub-threshold slope of 100 mV/decade whereas the experimental curve shows a low current and a poor slope of 1500 mV/decade. Fig. 3: 3D Simulation of the ZnO NWFET reported in [1]. This simulation used default parameters derived from literature ( Table 2).

Results and Discussion
The difference in currents and the subthreshold slopes indicates that the experimental device is greatly affected by defects. Therefore, defects were introduced into the modelled device. As stated, two types of defect were introduced which are fixed charge (Qf) and interface state charge (QIT). Fig. 4 shows simulated and experimental results after introducing defects with the parameters listed in Table 2. The fixed charge is kept at a low number value of 3.0 x 10 10 cm -2 which means it has little effect on the simulation. When this value is increased or decreased, it shifts the threshold voltage, but does not change the shape of the sub-threshold plot. Fig. 4 shows the main QIT parameters that were altered to fit. Nc300 was altered from 2.24 x 10 18 cm -3 to 5.31 x 10 18 cm -3 . ND is the donor concentration and is un-altered so as to keep it the same as the experimental value. NGA was altered from 9.0 x 10 16 cm -3 to 1.0 x 10 19 cm -3 and NTA was altered from 4.0 x 10 19 cm -3 to 9.0 x 10 20 cm -3 . The simulated device matches the measured device reasonably well at low currents. Fig. 4: 3D Simulation of the ZnO NWFET reported in [1]. Fixed charge and interface state charge were introduced into the simulation so as to fit the experimental results After introducing defects, the 'fit' between simulation and measurements is still poor at high currents, with the simulation predicting much higher currents than the experimental device. The most likely explanation for this discrepancy is contact resistance. There is therefore a need to simulate the effect of contact resistance. The device is simulated with different values contact resistance, varying from 10 Ω to 1.13 x 10 7 Ω. The simulation used a low fixed oxide charge of 3.0 x 10 10 cm -2 and high interface state trapped charge of 3.79 x 10 20 cm -3 which is derived from the above equations. To use the equations, 'E' is assumed to be 3.4 eV. Inserting parameters from Table  2, the value of QIT can then be derived. Fig. 5 shows a variation of contact resistance from Rcon1 = 10 Ω to Rcon5 = 8.0 x 10 10 Ω. The current remains constant from a contact resistance value of 0 Ω to 1.0 x 10 6 Ω, after that it sharply decreases. As can be seen from Fig. 5, contact resistance has negative impact on the electrical characteristics of NWFET. It reduces the voltage across the channel and thereby limits the maximum on-current. This result indicates that the experimental devices should have values of contact resistance less than about 1.0 x 10 6 Ω. It must be noted that the simulation assumed that the fabricated device process produced single crystal ZnO, but that is not the case as the etching process of the nanowire damages the nanowire and also the deposition process of ZnO on top of an insulating material, that is not lattice matched to the ZnO. This effect was not investigated here. Devedit can model polycrystalline materials, but this requires information on grain size and recombination parameters at grain boundaries.  [16]; (a) simulated and measured transconductance verses gate voltage (b) Simulated and measured transconductance Vs gate voltage for a device in which the series resistance has been de-embeded.
To complete the simulation work, transconductance graphs were derived and plotted. Fig. 6 (a) shows simulated and measured transconductance as a function of gate voltage. The simulation curve has peak transconductance of 8.52 x 10 -9 S at 36.8 V whereas the experimental curve has peak transconductance of 2.27 x 10 -8 S at 35.5 V. Using these peak values of transconductance, a field effect mobility (µFE) can be derived for both the simulated and experimental devices. The simulated device gives a µFE of 8.2 cm 2 /Vs which is comparable to the experimental value of 10.0 cm 2 /Vs.
The above values of mobility µFE include the effect of contact resistance and hence may underestimate the true mobility. However, the effect of contact resistance can be de-embedded by performing an identical simulation without any contact resistance. De-embedding in simulation is whereby the contact resistance is lowered to an insignificant value such 10 Ω. To reduce contact resistance under fabrication process, the channel doping can be increased while keeping the fabrication process the same. This implies that the surface charge and roughness will remain relatively the same as before as it depends on the etching techniques. The ZnO channel doping can be increased from 2.17x10 16 cm-3 to 1.0x10 18 cm -3 . Fig. 6 (b) shows that by de-embedding the device, the peak transconductance value is increased from 8.52 x 10 -9 S to 1.32 x 10 -7 S. The field effect mobility derived from this new value of transconductance is found to be 126.9 cm 2 /Vs, as summarized in Table 4. This is an excellent value that future work will aim for. This analysis indicates that the true mobility of the ZnO layer is much higher than that extracted from the measured transistor characteristics and is much closer to state-of-the-art values in ZnO devices. The de-embedded value is comparable to the state-of-the-art TFT by B. Bayraktaroglu, et al., [2]. Table  4 summarises the important characterisitics obtained through simulation.

Conclusion
3D Simulation was carried out and compared with a fabricated device. The experimental results had an oxide thickness of 100 nm and nanowire dimensions of length 10 µm, width 40 nm, and thickness of 36 nm. The device had the following electrical output characteristics: mobility value of 10.0 cm 2 /Vs at a drain voltage of 1.0 V, threshold voltage of 24 V and subthreshold slope (SS) of 1500 mV/decade. Using simulation, it was discovered that the experimental output results are degraded due to two main defects: contact resistance (Rcon ≈ 11.3 MΩ) and interface state trapped charge number of QIT = 3.79 x 10 15 cm -2 . De-embedding the contact resistance shows the device gives excellent field effect mobility of 126.9 cm 2 /Vs. Surface charge and roughness were not simulated due to limitations of the simulation software, but are hypothesized to contribute toward poor output characteristics.