Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 35-39

doi: 10.4028/p-4QkAFT

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-05

Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

Pavan Vudumula , Yu-Chieh Chien , Abdul Hannan Yeo , Lakshmi Kanta Bera , Umesh Chand , Voo Qin Gui Roth , Surasit Chung , Navab Singh , Yee-Chia Yeo

Institute of Microelectronics (IME), Agency for Science, Technology, and Research (A*STAR), Singapore 138634.

*E-mail: Vudumula_pavan_kumar@a-star.edu.sg, Chien_Yu_Chieh@a-star.edu.sg, channan_yeo@a-star.edu.sg, dLakshmi_kanta_bera@a-star.edu.sg,

Chand_Umesh@a-star.edu.sg, Roth_Voo@a-star.edu.sg, Surasit_chung@a-star.edu.sg, navab@a-star.edu.sg, Yeo_Yee_Chia@a-star.edu.sg,

Keywords: Channeling implant, Deep p-body, Single step implant

Abstract

In this work, TCAD simulation of SiC MOSFETs design with deep ( ) p-base using single step aluminum channeling implant along [0001] direction and JFET design using phosphorus implant is presented. The threshold voltage ( ) was around 3 V for both the devices. Improvements to the specific on-resistance ( ) reduction by , breakdown voltage (BV) enhancement by , miller plateau reduction by is reported. Furthermore, both the Baliga figure-ofmerit (BFOM) ( ) and high-frequency figure-of-merit (HFOM) ( ) with deep p-base/JFET implant are enhanced as compared to shallow p-base/JFET implant. This paper provides valuable insights into the advantages of a single-step channeling implant at room temperature, without the need for a hard mask. This approach offers a high throughput with a lowcost process for fabricating high-performance SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

4H-SiC MOSFETs are well-suited for hybrid electric vehicles (HEV) and pure electric vehicles (EV) with a voltage rating of 1.2 kV . This is attributed to their impressive BV, low , and fast switching speeds . These devices consist of box-shaped implantation profiles formed through multi-step processes, including the p -base, JFET, and regions. Aluminum is used for both the p -base and implantation, while phosphorus is used for the JFET and implantation [2]. The multi-step implantation for box profiles is commonly conducted utilizing hard masks at high temperatures ( ). Undoubtedly, this process entails several steps that inherently impede manufacturing throughput. Few studies have investigated the impact of deep p-body and deep JFET on and short circuit withstand time [3,4]. A recent study has shown that a well-defined box-type profile can be achieved through a single-step implantation with significant depth along the [0001] and [11 ] crystal orientations [5]. However, the box shape profile is more effective in the [0001] direction. The channeling implantation process performed at room temperature, allows the use of photoresists which eliminates the need for hard mask processes. This helps to streamline fabrication by eliminating several steps involved in hard mask patterning which could lead to significant cost reductions. This channeling implant has potential applications in SiC super junction devices too. However, there are little reports on the characteristics of deep p-body standard SiC MOSFETs using single-step implant. This study investigates the impact of a deep p -body using a single-step implant profile along [0001] and the corresponding JFET implant design using phosphorous channeling implant along [0001] in 1.2 kV MOSFETs in terms of its static and dynamic characteristics.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

Experimental data on aluminum channeled implantation with an energy of 300 keV and a dose of along the [0001] crystal direction show a nearly box-shaped profile up to a depth of [4]. This profile has been used for the p-body. To achieve a uniform JFET design, phosphorus implantation with optimized parameters (energy: , dose: ) is necessary. The implant profile is illustrated in Fig. 1.

Fig. 1 Simulated doping profile for deep channeling implantation along [0001] orientation with optimized JFET profile.

Fig. 1. Simulated doping profile for deep channeling implantation along [0001] orientation with optimized JFET profile.

Fig. 2 Schematic of (a) non-channeled p-base and (b) channeled single-step implanted p-base from TCAD simulation.

Fig. 2. Schematic of (a) non-channeled p-base and (b) channeled single-step implanted p-base from TCAD simulation.

The device cross-section of a 1.2 kV MOSFET with a non-channeled implant for a p-body depth of and a p-body depth of using channeling implant is depicted in Fig. 2 (a) and (b), respectively. These devices are simulated using TCAD with
, and a uniform epitaxy doping profile of . The extracted threshold voltage ( ) is approximately 3 V for both devices, and specific on-resistance ( ) from characteristics (Fig. 3 (a)) is lower with a JFET implant depth of compared to a shallow JFET implant depth of . This reduction is due to charge sustaining layer (CSL) with deep JFET implant, resulting in increased electron flow and thus a lower . Fig. 3 (b) demonstrates a improvement in blocking voltage for the p-body device with a depth of compared to the device with a depth of . Enhanced two-dimensional electric field distribution with deeper p-body compared to shallow p-base allows the device to sustain higher blocking voltages. Deep p-base better shields the channel and gate oxide from high drain bias due to the depletion in JFET.

Fig. 3 Simulated (a) output and (b) blocking voltage characteristics for SiC MOSFETs with nonchanneling (orange) and channeling (blue) implantation.

Fig. 3. Simulated (a) output and (b) blocking voltage characteristics for SiC MOSFETs with nonchanneling (orange) and channeling (blue) implantation.

Fig. 4 Blocking-state electric field distribution near breakdown for (a) non-channeling and (b) channeling p-base region in SiC MOSFETs.

Fig. 4. Blocking-state electric field distribution near breakdown for (a) non-channeling and (b) channeling p-base region in SiC MOSFETs.

Fig. 5 Simulated (a) gate charge and (b) switching characteristics with non-channeling and channeling p-base region in SiC MOSFETs.

Fig. 5. Simulated (a) gate charge and (b) switching characteristics with non-channeling and channeling p-base region in SiC MOSFETs.

The off-state electric field distributions near the breakdown regime for and for -base are shown in Fig. 4 (a) and 4 (b). Additionally, gate charge (Fig. 5(a)) and clamped inductive load switching simulations (Fig. 5 (b)) are performed using a mixed-mode SPICE environment to analyze the miller plateau and switching losses. The non-linear capacitance simulations with variations in drain bias, including input ( ), output ( ), and reverse transfer ( ) capacitances are shown in Fig. 6. An improvement in corresponds to the reduced gate-to-drain coupling with the deep p-base design, which induces an increased depletion width along the JFET region during the switching regime. and remain the same for both devices as the remaining regions remain unaltered with a cell pitch. Table 1 lists the performance metrics (BFOM, HF-FOM) and switching losses for both devices along with benchmarking results.

Fig. 6 Simulated non-linear input, output, and miller capacitances with drain bias with nonchanneling and channeling p-base region in SiC MOSFETs.

Fig. 6. Simulated non-linear input, output, and miller capacitances with drain bias with nonchanneling and channeling p-base region in SiC MOSFETs.

Table 1 Simulated electrical performance metrics ( BFOM and ) at and .

0.7 μm p-base 1.2 kV 4H-SiC MOSFET
2.0 μm p-base 1.7 kV 4H-SiC MOSFET
Benchmark [Ref. 3]

T (°C)
BV (V)
Ron,sp
(mΩ-cm²)
BFOM
(MV/cm²)
T (°C)
BV (V)
Ron,sp
(mΩ-cm²)
BFOM
(MV/cm²)

27
1208
2.4
608
27
1693
1.7
1686
WJFET = 0.9 μm
Lch = 0.5 μm
Ldrift = 10 μm
Ndrift = 8×10¹⁵ cm⁻³

150
1220
2.7
551
150
1700
2.0
1445

Qgd
(nC/cm²)
Ron,sp
(mΩ-cm²)
HF-FOM
(nC-mΩ)

Qgd
(nC/cm²)
Ron,sp
(mΩ-cm²)
HF-FOM
(nC-mΩ)

27
117
2.4
281
27
82
1.7
140

150
117
2.7
433
150
82
2.0
164
Electrical parameters:
Ron,sp = 4 mΩ-cm²
BV = 1560 V

Eon (mJ)
Eoff (mJ)

Eon (mJ)
Eoff (mJ)

27
2.1
0.8
27
1.7
0.8

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

In this study, we showed that the single-step channeling implantation is a highly promising method for realizing high BFOM and low in MOSFETs. In addition, the implementation of channeling implantation ensured a superior process throughput at a much lower cost than the standard multi-step implant process.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

This work was supported by the Science and Engineering Research Council of A*STAR (Agency for Science, Technology and Research) Singapore, under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

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D. Kim and W. Sung, "Improved short-circuit ruggedness for 1.2 kV 4H-SiC MOSFET using a deep p-well implemented by channeling implantation," IEEE Electron Device Letters, vol. 42, no. 12, 1822-1825 (2021).

M. K. Linnarsson, L. Vines, and A. Hallén, "Influence from the electronic shell structure on the range distribution during channeling of ions in ," J. Appl. Phys., 130, 075701 (2021).

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