Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 41-50

doi: 10.4028/p-4FJgLU

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-18

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-05

Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

Ahmad Abbas , Cyrille Le Royer , Romain Laviéville , Jérôme Biscarrat , Guillaume Gelineau , Frédéric Allibert , Edwige Bano , and Philippe Godignon

Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France

Soitec S.A., Parc technologique des fontaines, 38190 Bernin, France

Univ. Grenoble Alpes, USMB, CNRS, Grenoble INP, CROMA, France

ahmad.abbas@cea.fr, cyrille.leroyer@cea.fr, romain.lavieville@cea.fr,

jerome.biscarrat@cea.fr, guillaume.gelineau@cea.fr, frederic.allibert@soitec.com,

edwige.bano@grenoble-inp.fr, philippe.godignon@cea.fr

Abstract

In this work, we investigate the static electrical parameters of power diodes with various designs and architectures (Schottky, PiN, and JBS with hexagonal or stripes anode), fabricated on two types of 150 mm substrates (single crystal 4H-SiC reference and 3C-poly silicon carbide based substrates: ). I(V) measurements are carried out in both reverse and forward modes to assess the impact of designs and substrates. Non-destructive avalanche mode is reached with similar performance (leakage, ) observed for both substrates (due to identical drift layers and device structures). All diode designs on SmartSiC exhibit a larger current conduction and less resistance in the ohmic regime (compared to bulk), whatever the temperature (up to ). Partitioning model is also proposed for evaluating the substrate contribution on the measured specific resistance and on the observed SmartSiC gains.

Introduction

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Bulk substrates growth requires a long, energy-intensive and costly process, which limits the availability of SiC substrates for devices production today. Consequently, 3C-poly silicon carbide based substrates ( pSiC ) are currently being considered as an alternative substrate for SiC power devices fabrication. By utilizing the SmartCut technology, a high-quality layer can be bonded (conductive bonding) on top of a thick polycrystalline SiC handle wafer [1]. The resulting SmartSiC substrates are engineered to achieve better device yield and to optimise conduction losses [2] because of the low resistivity poly-SiC layer, thanks to one order of magnitude lower resistivity values compared to mono-SiC. SmartSiC not only enhances electrical performance but also reduces manufacturing costs and environmental impact. It enables the reuse of donor wafers, yielding around 500 wafers per SiC boule, ten times more than standard methods [3]. In this work, we study the impact of temperature on the static electrical parameters of 1200 V power diodes with various designs and architectures (Schottky, PiN, JBS with hexagonal cells or stripes) fabricated on 150 mm bulk and based substrates (SmartSiC ).

Devices Fabrication

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Three power diodes architectures (Schottky, PiN, and JBS: Fig. 1a-b) have been fabricated through a process flow designed for 1200 V blocking voltage capability [4], with Al implanted p+ guard rings and a junction termination extension (JTE) annealed at to achieve the breakdown voltage target (Fig. 1c). Various anode and edge terminations have been designed and fabricated on both 4 H SiC bulk and SmartSiC substrates (Fig. 1d). The substrates have not been thinned and backside contact formation was performed using laser annealing [5].
I(V) measurements, conducted in both reverse and forward modes, are aimed at evaluating the impact of different designs and substrates.

Fig. 1. Description of the tested diodes samples (device designs: Schottky, PiN, and JBS). a) Top view, b) anode cross-section with c) edge termination cross-section at the diode periphery, d) Additionally, standard bulk and new substrates have been considered for building the diodes samples on these two types of epiwafers (with identical epi process, designed for 1200 V rating).

Fig. 1. Description of the tested diodes samples (device designs: Schottky, PiN, and JBS). a) Top view, b) anode cross-section with c) edge termination cross-section at the diode periphery, d) Additionally, standard bulk and new substrates have been considered for building the diodes samples on these two types of epiwafers (with identical epi process, designed for 1200 V rating).

Electrical Characteristics: Off-State

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Off-state characteristics, shown in Fig. 2a, highlight various reference diode types that are reverse biased on single crystal (bulk) and epiwafers. Diodes on both epiwafers achieved non-destructive avalanche mode with similar leakage currents and avalanche voltages (VAV), attributed to the identical drift layers and device structures.

Fig. 2. a) Reverse I(V) curves (wafer median for bulk and SmartSiC ) for Schottky, JBS (hexagonal and stripes) and PiN. Anode surface is . b) Corresponding box plots of reverse leakage current densities J extracted at 1200 V (for PiN, JBS with stripes, and Schottky diodes on SmartSiC and bulk), c) examples of wafermaps for J @ 1200 V .

Fig. 2. a) Reverse I(V) curves (wafer median for bulk and SmartSiC ) for Schottky, JBS (hexagonal and stripes) and PiN. Anode surface is . b) Corresponding box plots of reverse leakage current densities J extracted at 1200 V (for PiN, JBS with stripes, and Schottky diodes on SmartSiC and bulk), c) examples of wafermaps for J @ 1200 V .

In Fig. 2b, the leakage current density is extracted at 1200 V (before avalanche). We observe similar leakage current distributions for both substrates (for PiN, JBS and Schottky diodes). Fig. 2c shows the wafer mapping of this leakage current level extracted for JBS (with stripes) on both bulk and SmartSiC substrates. Both substrate types reveal similar leakage current profile, with an increased leakage for a limited number of sites situated around the center and edges of the wafer, due to the presence of defects in these areas. It is also worth noting that the levels of reverse leakage current around the centre are slightly reduced for SmartSiC substrates. Wafer mapping and yield analysis indicated that defects contributing to off-state performance degradation, such as BPDs or TEDs, were minimally influenced by the substrate material [6].

Electrical Characteristics: On-State

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Following the off-state study, forward mode measurements are carried out. I(V) characteristics of SmartSiC and bulk devices are compared. JBS diodes on SmartSiC exhibited superior current conduction and reduced resistance in the ohmic regime (Fig. 3a), demonstrating the impact of substrate resistivity. The specific differential resistance ( ) was extracted as illustrated in Fig. 3a. In Fig. 3b, decreases as the Schottky surface ratio increased for both bulk and SmartSiC , with a notable reduction in resistance observed in hexagonal configurations. All diodes fabricated on SmartSiC exhibited less resistance than their bulk counterparts.

Fig. 3. a) Example of JBS diodes I(V) measurements for bulk and SmartSiC (with specific differential resistance definition). b) Extracted Rdif for different JBS diode designs (+Schottky) as function of the Schottky surface ratio.

Fig. 3. a) Example of JBS diodes I(V) measurements for bulk and SmartSiC (with specific differential resistance definition). b) Extracted Rdif for different JBS diode designs (+Schottky) as function of the Schottky surface ratio.

Fig. 4 shows the JBS Ron-BV figure of merit for the studied JBS samples with a comparison to state-of-the-art diodes [7]. For breakdown voltage (BV) ratings between 1400 and 1600 V , we observe that the specific on-resistance (similarly extracted as ) is reduced and is closer to the theoretical limit of for the SmartSiC JBS compared to the bulk reference and also to state-of-the-art JBS devices (including commercial devices with thinned substrates) [7].

Fig. 4. JBS specific ON resistance versus breakdown voltage (for the investigated bulk and SmartSiC hexagonal JBS diodes, compared to state-of-the-art JBS diodes, including commercial products) [7].

Fig. 4. JBS specific ON resistance versus breakdown voltage (for the investigated bulk and SmartSiC hexagonal JBS diodes, compared to state-of-the-art JBS diodes, including commercial products) [7].

On-state resistance behaviour with temperature

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The forward characteristics were further studied as a function of temperature. The observed conduction gain for the SmartSiC samples (compared to bulk) was investigated from to in Fig. 5 and Fig. 6.

Fig. 5 shows measurements for JBS diodes (with stripes) on bulk and SmartSiC epiwafers, with an observed exponential behaviour. The absolute difference between bulk and is (respectively ) at (resp. ).

Fig. 5. Impact of temperature ( ) on measured specific differential resistance ( ) for JBS diode (reference design with stripes). For both samples, the data can be fitted using an exponential model (as observed for results in [8], cf. Fig. 7).

Fig. 5. Impact of temperature ( ) on measured specific differential resistance ( ) for JBS diode (reference design with stripes). For both samples, the data can be fitted using an exponential model (as observed for results in [8], cf. Fig. 7).

In order to check if this advantage offered by SmartSiC exist also for the other diodes types, we perform similar comparison for the following designs:

JBS with stripes: three designs with various Schottky ratios

JBS with hexagonal cells

Reference Schottky diode

The following figures show extracted versus temperature for these five different diode designs on SmartSiC epiwafer (Fig. 6a) and on bulk epiwafer (Fig. 6b): again, an increasing trend with temperature can be observed for all samples. Besides a minor dispersion between the designs is also highlighted ( ). In Fig. 6c, the differential resistance gain, , between the two epiwafers is calculated and plotted against temperature. The gain offered by SmartSiC epiwafer compared to bulk counterpart is found to be independent on the diode design: (respectively ) at (resp. ).

Fig. 6. a-b) Comparison of for different diodes (JBS with three stripes designs; hexagonal cells JBS, and Schottky) for bulk and SmartSiC epiwafers, c) and corresponding differential resistance gain (bulk-SmartSiC) versus temperature showing identical trend for all diode designs.

Fig. 6. a-b) Comparison of for different diodes (JBS with three stripes designs; hexagonal cells JBS, and Schottky) for bulk and SmartSiC epiwafers, c) and corresponding differential resistance gain (bulk-SmartSiC) versus temperature showing identical trend for all diode designs.

Fig. 7 reveals that all device designs, regardless of epi or substrate (including additional 1700 V epiwafer with the same diode process [4], and literature reference [8]), follow the same predictive behaviour: values at exactly reflect at . This indicates that the model from Fig. 5 can be applied to all these various device/substrate/epi configurations (with very similar To parameter).

Fig. 7. Measured differential resistance at versus for various JBS designs (+Schottky) on different sites (for two wafers with same 1200 V epi, +1700 V bulk epiwafer). Ref [8] bulk data are in agreement with the observed trend.

Fig. 7. Measured differential resistance at versus for various JBS designs (+Schottky) on different sites (for two wafers with same 1200 V epi, +1700 V bulk epiwafer). Ref [8] bulk data are in agreement with the observed trend.

Discussion

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The focus on this paper is to highlight on-resistance difference in the forward operation mode of unipolar 1200 V diodes fabricated on bulk and SmartSiC epiwafers. For the off-state characteristics depicted in Fig. 2, the findings suggest that for the same diode device and epi designs on bulk and SmartSiC , the off-state performance ought to be similar in terms of reverse leakage current levels and non-destructive avalanche breakdown. This also suggests that SmartSiC in the reverse mode
behaves similarly to bulk wafers, which also implies that the engineered substrate does not exhibit additional defects.

In the on-state, differential resistance ( ) has been comprehensively studied between Schottky and several JBS diode designs. The overall forward conduction current in Fig. 3 illustrates the advantage of using SmartSiC to reduce conduction losses with a less resistive handle substrate as reported in [9]. This confirms the influence of substrate resistivity on the on-state performance of power devices. The exponential temperature dependence of demonstrated in Fig. 5 to 7, coupled with the increased absolute difference at further highlight the SmartSiC substrate's stability at high-temperature, which is reported here for the first time.

Further calculations are performed to anticipate and compare the performance of against thinned bulk epiwafers. This requires a decomposition of the different resistance contributions of the diode. Fig. 8 presents the differential resistance partitioning model used, cf. Eq. 1. To avoid additional calculation terms that may emerge from the current spreading in JBS devices, Schottky diodes is preferred here. The three main contributors to the total differential resistance are the epilayer (drift + buffer), substrate, and contacts (anode and cathode) resistances. The resistivity of each layer (Eq. 2, Eq. 3, Eq. 4) is calculated according to Eq. 5 (sheet resistivity) and Eq. 6 (electron mobility). For the electron mobility, Arora model [10] was used with parameters calibrated from [11] for 4H-SiC and from [12] for 3C-poly SiC . The contribution of the contacts is calculated as the resistance contributions deducted from the extracted measured differential resistance.

Fig. 8. Vertical SiC diode differential resistance partitioning model is composed of three primary contributors: epilayer (comprises drift and buffer layers), contacts (anode and cathode), and substrates (bulk vs. SmartSiC ). Arora model [10] for electron mobility is used to calculate the resistivity of each layer and construct the final partition.

Fig. 8. Vertical SiC diode differential resistance partitioning model is composed of three primary contributors: epilayer (comprises drift and buffer layers), contacts (anode and cathode), and substrates (bulk vs. SmartSiC ). Arora model [10] for electron mobility is used to calculate the resistivity of each layer and construct the final partition.

partitioning is calculated for both and bulk epiwafers in addition to a thinned down version of the bulk substrate at and temperatures as shown in Fig. 9. It is observed that SmartSiC substrate ( , without thinning) exhibited lower resistance even compared to thinned bulk epiwafer. Furthermore, these calculations bring new insights on the extracted shown in Fig. 6c: the gain can be attributed to the substrate ( ) and partially to the back side contact ( , as the anode and epi components are identical for both samples.

Fig.9. RDIF partitioning calculations at a) and b) for Schottky diodes with same epi. For bulk epiwafer, is reduced with substrate thinning. SmartSiC substrate enables further reduction without thinning.

Fig.9. RDIF partitioning calculations at a) and b) for Schottky diodes with same epi. For bulk epiwafer, is reduced with substrate thinning. SmartSiC substrate enables further reduction without thinning.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

This study compares 1200 V 4H-SiC power diodes on two different substrate technologies (single crystal reference bulk and 3 C -poly silicon carbide based substrates: SmartSiC ). The reverse mode measurements demonstrate that substrate material has a minimal impact on defect propagation affecting off-state performance, as both bulk and SmartSiC exhibit similar nondestructive avalanche characteristics due to identical drift layers and device structures. The specific differential resistance ( ) decreases with an increase in Schottky surface ratio, with hexagonal configurations yielding the lowest resistance, particularly in samples. JBS diodes fabricated on SmartSiC showed superior current conduction and lower resistance in the ohmic regime, highlighting the significance of substrate resistivity. The results also reveal an exponential temperature dependence of , indicating that substrate properties, including thickness, play a crucial role in high-temperature device performance.
Overall, introducing SmartSiC enables to optimize device performance (reducing specific onresistance even at high temperature) while sustaining similar off-state behaviour compared to standard bulk. This study paves the way for further investigations related to dynamic performance and reliability/ruggedness to consolidate the SmartSiC position in power electronics.

Funding

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

This project has received funding from the Key Digital Technologies (KDT) under Grant Agreement No 101007237 (TRANSFORM). The KDT receives support from the European Union's Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

The authors would like to express their sincere gratitude to the other members of the research team: Dr. Julie Widiez, Saliou Gningue from CEA-Leti for data interpretation and assistance in electrical measurements; Dr. Séverin Rouchier and Dr. Walter Schwarzenbach from Soitec for substrates preparation and discussion on results. Their expertise and commitment were instrumental in the realization of our research objectives.

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The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

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