Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 69-74

doi: 10.4028/p-NADj0f

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-05

-SiC VDMOSFET Having On-Current Improvement

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

Y. Widjaja , V. Nebesnyi , A. Asenov , N. Xeni , I. Topaloglu , D. Bensouiah , S. Rathi , R. Young , L. Laborie , Y. Qi , M. Bell , D.T. Clark

VoltA Semiconductor, Inc., Cupertino, CA, USA

Semiwise Ltd., Glasgow, UK

Clas-SiC Wafer Fab Ltd., Lochgelly, UK

ª*ywidjaja@voltasemi.com, vn@voltasemi.com, asen.asenov@semiwise.uk, nikolas.xeni@semiwise.uk,

servin.rathi@clas-sic.com, robert.young@clas-sic.com, ileo.laborie@clas-sic.com,

Keywords: 1200 V , Silicon Carbide, Iow specific on-resistance, on-current improvement, p-well bias.

Abstract

We experimentally demonstrated on-current improvement on VDMOSFET fabricated in a standard 1200 V -rated based VDMOSFET. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A ratio between the on-current gain and the p -well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

SiC has been increasingly used in high-voltage, high-power applications due to its high critical electric field. Improvements in the on-current and specific on-resistance are continuously being sought after through various methods, such as process optimizations [1-3], cell topologies [4], and charge modulations [5]. In this work, we experimentally demonstrated on-current improvement on 1200 V-rated 4H-SiC based VDMOSFET.

Fig. 1(a) illustrates a schematic cross-sectional view of our device, which is fabricated in a standard 1.2 kV 4 H -SiC process. A breakdown voltage of 1500 V is obtained as shown in Fig. 1(b). Typical aluminum and nitrogen implants were used for -well and , respectively. These implants were activated by a high temperature annealing with a carbon cap layer. Gate dielectric was fabricated, including passivation of interface and oxide traps. The front ohmic contacts to were enabled via a self-aligned nickel silicidation. A power metal stack, consisting of , was used to form metallization. For the ohmic back contact, the deposited metal was laser annealed to form an ohmic contact followed by a solderable back metal stack.

Fig. 1.(a) Cross-sectional view of the 1.2 kV VDMOSFET device structure (b) Breakdown characteristic of typical 1.2 kV device

Fig. 1. (a) Cross-sectional view of the 1.2 kV VDMOSFET device structure (b) Breakdown characteristic of typical 1.2 kV device

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

In this work, separate contacts are formed for the p -well and source regions, allowing for independent biasing of the p -well and source regions. A positive bias is applied to the p -well region when the VDMOSFET is in the on-state and is removed when the VDMOSFET is in the off-state. In a conventional VDMOSFET, the p-well and source regions are shorted and typically connected to a common ground.

Fig. 2(a) shows the transfer curves measured from a test structure having a JFET width of with different voltage applied to the p -well region for different Vds. The ratio of the VDMOSFET drain current with and applied to the p -well region for a range of applied gate voltage is shown in Fig. 2(b). As shown in Figs. 2, the drain on-current with a positive bias applied to the p -well region is 2.5 x higher than a conventional VDMOSFET (with applied to the p -well region). The ratio of the drain on-current as a function of applied Vp bias is also shown in Fig. 2(c), indicating that the amount of current flow across the VDMOSFET can be controlled by both gate voltage Vg and p-well bias Vp.

Fig. 2. (a) Transfer curve of VDMOSFET for and 2 V with (solid) and (dashed) (b) Ratio of drain current with and applied, demonstrating the on-current gain with applied (c) Ratio of drain current at different applied Vp and for .

Fig. 2. (a) Transfer curve of VDMOSFET for and 2 V with (solid) and (dashed) (b) Ratio of drain current with and applied, demonstrating the on-current gain with applied (c) Ratio of drain current at different applied Vp and for .

Fig. 3(a) shows the associated p -well current, demonstrating that the large on-current gain does not require large p -well current. The ratio between on-current gain to the p -well current can be calculated to be and is shown in Fig. 3(b). Fig. 4 shows the corresponding transconductance (gm) curves. As the results show, both threshold voltage (Vth) shift and gm increase contribute to the on-current gain. When the VDMOSFET is turned off, the positive bias is removed and the off-state characteristics, including Vth, return to that with applied.

Fig. 3. (a) p -well current of VDMOSFET for with different applied Vp (b) Ratio of oncurrent gain (the difference between drain current with and ) and p -well current for .

Fig. 3. (a) p -well current of VDMOSFET for with different applied Vp (b) Ratio of oncurrent gain (the difference between drain current with and ) and p -well current for .

Fig. 4. Transconductance (gm) curves of VDMOSFET for Vd=2V with different applied Vp.

Fig. 4. Transconductance (gm) curves of VDMOSFET for Vd=2V with different applied Vp.

TCAD simulations are performed to study the underlying mechanisms of the drain on-current gain. The TCAD simulations are first calibrated to match the experimental results for the condition. When a positive bias is applied in the TCAD simulations, it similarly shows the on-current gain observed in experiments. Fig. 5 illustrates a comparison of the transfer curve from the TCAD simulations and the measurement results.

Fig. 5. Comparison of measured (solid) and TCAD simulation (dashed) results of VDMOSFET transfer curve for with different applied Vp .

Fig. 5. Comparison of measured (solid) and TCAD simulation (dashed) results of VDMOSFET transfer curve for with different applied Vp .

Fig. 6 shows the current density of the VDMOSFET with and , respectively. When a positive bias is applied, the conduction area encompasses the source junction area and no longer limited to the area of the channel region. The additional conduction paths are not limited by the channel mobility, as can be seen from the higher transconductance in Fig. 4.

Fig. 6. TCAD analysis of total current density with (a) and (b) .

Fig. 6. TCAD analysis of total current density with (a) and (b) .

The improvement in the current flow due to increased conduction area can reduce temperature rise due to current crowding. Therefore, although a higher current density is achieved with positive Vp bias, the short circuit capability is not expected to degrade. The additional current path through the source junction region may be considered as bipolar junction transistor (BJT) current. As previously reported, BJTs typically exhibit better short-circuit capability than MOSFETs. [6, 7]

Further process improvements on the conventional SiC VDMOSFET and JFET width optimization have resulted in lowering on-state resistance Rds,on to (Fig. 7). Using the p-well biasing technique described in this work, low Rds, on of can be achieved.

Fig. 7. Specific on-resistance for different JFET width and layouts.

Fig. 7. Specific on-resistance for different JFET width and layouts.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

The experimental results presented in this study highlight a significant advancement in the performance of 1200 V -rated 4H-SiC VDMOSFETs through the application of a positive bias to the p -well region. This technique led to more than a 2.5 x improvement in on-current while maintaining a low p-well current, with a remarkable ratio between on-current gain and p-well current. The TCAD simulations provided insights into the mechanisms responsible for this improvement, illustrating the expansion of the conduction area beyond the channel region when a positive bias was applied, thereby reducing the impact of channel mobility limitations. Additionally, the results showed that this technique could reduce the specific on-resistance to , a substantial improvement over conventional device. These findings underscore the potential of p-well biasing as a critical method for enhancing the performance of SiC-based power devices. Further research and process optimizations, for example in JFET width optimization and other design aspects, could unlock even greater performance gains, advancing the efficiency and capability of SiC devices in high-power applications.

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The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

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