Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 83-88

doi: 10.4028/p-vHPv5Z

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Revised:
2025-02-06

Accepted:
2025-08-04

Online:
2025-09-08

Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

The original version of this paper is available on https://www.scientific.net/KEM.1022.83.pdf

Ayan K. Biswas , Daniel J. Lichtenwalner , Brett Hull , Donald A. Gajewski and Satyaki Ganguly

Wolfspeed, Inc, 4600 Silicon Drive, Durham, NC 27703, USA

ayan.biswas@wolfspeed.com, daniel.lichtenwalner@wolfspeed.com brett.hull@wolfspeed.com, don.gajewski@wolfspeed.com, satyaki.ganguly@wolfspeed.com

Keywords: SiC MOSFETs, Accelerated Reverse Bias (ARB), Lifetime modeling, Gate Oxide Reliability, Accelerated HTRB.

Abstract

Robustness under blocking is an important reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, which typically employs multiple VDS stress values beyond the rated drain bias but below the avalanche voltage, is considered as the best practice for measuring the device lifetime in the blocking mode. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified modeling approach where qualification-like high temperature reverse bias (HTRB) or ARB test at a single stress voltage for a reasonable stress duration can be used to project gate oxide lifetimes under blocking.

Introduction

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Owing to its wider bandgap allows fabrication of unipolar power switches with voltage ratings more than ten times higher than is feasible for Si unipolar devices, with the same specific onresistance. Hence during off state while blocking high voltage, the electric fields experienced by SiC and the gate dielectric (typically ) are much higher in SiC vertical power MOSFET devices as compared to their Si counterparts [1]. As a result, reliability under blocking has become a hot topic for MOS based SiC power devices and is discussed in detail by industry standard bodies such as JEDEC. Although running only a single point high temperature reverse bias (HTRB) qualification test at or near maximum rated drain bias and at maximum rated junction temperature can fulfill the qualification requirements for blocking reliability, it does not provide information regarding device lifetime prediction for SiC-MOS devices during high voltage off-state stress. Like gate bias mediated TDDB, under high drain bias stress failures are typically due to gate oxide wear-out in the JFET region of the power device. In order to enable blocking lifetime extrapolation at operating condition, a modeling approach consistent with the E-model for gate oxide (Gox) lifetime can be used for accelerated reverse bias (ARB) stressing. For ARB stressing one would typically employ multiple stress values beyond the rated drain bias but below the avalanche voltage [2-5]. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified alternative modeling approach that can be used from ARB/HTRB test data from one stress drain voltage and reduced stress time, to project device lifetime under blocking at lower drain voltage values.

Experimental Data on Accelerated Reverse Bias (ARB) Test

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SiC power MOSFETs are designed with a safe margin between rated voltage and avalanche voltage which enables the accelerated reverse bias (ARB) test to be performed above the rated drain voltage, but below the avalanche voltage of the device. This margin is critical as it determines how much voltage acceleration can be generated above the rated voltage. In this regime of drain stress,
oxide electric field in the JFET gap can induce gate oxide wear-out failures. Figure 1 shows the results of an ARB test where three sets of Wolfspeed 1200 V rated packaged parts were stressed with values of and 1450 V at for nearly one year to gather failure statistics. The devices show relatively low gate and drain leakage until abrupt drain to gate/source short failure occurs, with little to no precursor signal, similar to what happens in a constant bias time dependent dielectric breakdown (TDDB) test.

Fig.1. MTTF lifetime projection of 1200 V rated SiC MOSFETs under ARB condition from three groups of stressed parts at . Inset shows a cross-sectioned device with a gate oxide rupture after ARB stress right at the highest field point, in the center of the JFET region.

Fig.1. MTTF lifetime projection of 1200 V rated SiC MOSFETs under ARB condition from three groups of stressed parts at . Inset shows a cross-sectioned device with a gate oxide rupture after ARB stress right at the highest field point, in the center of the JFET region.

Failure analysis confirms that the ARB failure mechanism is gate oxide breakdown at the center of the JFET gap (inset in Fig. 1). This is expected because that is the location of the highest gate oxide electric field in an ARB test. There is no evidence of edge termination or SiC breakdown, which demonstrates that gate oxide wear-out is the primary failure mechanism. Therefore, from the failure distribution which followed Weibull statistics, lifetime projection at operating voltage is then performed by extracting fitting parameters via maximum likelihood estimation and employing a "linear E-model". The median time to failure (MTTF) plot is derived from the ARB dataset and indicated as in Fig. 1.

Lifetime Modeling for ARB

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Although the above mentioned method is the best possible approach to model ARB data, it has been extremely time consuming to take a certain percent of population to failure for all different drain bias values such that lifetime can be projected with a sufficiently high confidence level. Simply from the perspective of test-duration, conducting an ARB test similar to the one presented Fig. 1 for every qualification of a new product is not feasible. Therefore, we propose a modeling approach that allows one to project blocking lifetime within a reasonable amount of test duration while maintaining a high confidence level. Figure 2 portrays this alternative approach for off-state lifetime modeling utilizing the "linear E-model" and a single stress voltage failure data set obtained from a qualification type HTRB or ARB test running for a certain duration (preferably 1000 hours or more). Considering that a certain percentage ( ) of the population failed after is applied for hours, with a known Weibull slope ( ), MTTF or any other failure time percentile ( ) can be extrapolated ( ) at that condition as given by Eq. 1. From this test result, according to "linear E-model" a blocking lifetime curve can be drawn for any drain bias using Eq. 2.

However, such an estimation will still need the knowledge of either voltage acceleration or intercept . Estimation of is non-trivial and equally challenging as constructing lifetime curves from multiple drain biases. Conversely, the intercept represents the lifetime of a device when is extrapolated to 0 . At zero gate or drain bias the Gox lifetime is likely determined by the physics of diffusion and subsequent degradation mechanism. Hence the conjecture that at for a given device technology (identical oxide thickness, drift thickness, cell design etc.) and temperature likely should hold at least for a first order approximation. By using this argument, we propose to extract value by conducting TDDB test on the devices from the same product family with multiple voltages. Thus, the knowledge of value from a TDDB test, along with a known Weibull slope ( ) likely can be utilized to construct a blocking lifetime curve for any failure percentile from a single drain bias stress test data.

Fig. 2. Schematic representation of blocking lifetime plot construction from a single stress for hours. Estimation of failure time for any failure percentage ( ) from stress time with a certain failure percentage ( ) and the knowledge of provides a means to construct the TTF extrapolation line.

Fig. 2. Schematic representation of blocking lifetime plot construction from a single stress for hours. Estimation of failure time for any failure percentage ( ) from stress time with a certain failure percentage ( ) and the knowledge of provides a means to construct the TTF extrapolation line.

Analysis of TDDB data for

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In the previous section, we argued at gate oxide lifetime should solely be determined by the physics of diffusion at a particular temperature and thereby making comparable to . A relevant question can be whether experimental data supports this claim. To address this, we extracted values from a significant number of TDDB tests conducted at multiple gate voltages ( ) on different sets of devices with similar voltage ratings, all with comparable gate oxide thicknesses. By extracting fitting parameters via maximum likelihood estimation and employing a "linear E-model", MTTF lifetimes for different products are plotted in Fig. 3. values projected from TDDB data fall within the range of hours. Notably, value ( hours) extracted from the year-long ARB test (as shown in Fig. 1) closely matches with the value obtained from TDDB testing on similar devices at , further corroborates this assumption.

Fig. 3. MTTF ( ) lifetime plots for TDDB tests on different products having similar gate oxide thickness and similar voltage and resistance ratings.

Fig. 3. MTTF ( ) lifetime plots for TDDB tests on different products having similar gate oxide thickness and similar voltage and resistance ratings.

Discussion of Different Scenarios under ARB Test

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Fig. (4a-d) presents hypothetical scenarios of projecting MTTF from a 1200 V rated product, assuming zero failures after 1000 hours of stressing, for different , sample size and values. In Fig. 4(a), values are varied from to hours with a value of 1 and a sample size of 240 . In case of 0 failures out of 240 , the failure percentage ( ) at the stress condition is calculated using equivalent failure rate at a confidence level ( ), yielding a failure rate of . Substituting the value of and stress time hours into Eq. 1, is obtained, as indicated by the yellow circle. MTTF lines are drawn by connecting the yellow circle to different values. A higher value from positive gate bias TDDB suggests a longer intrinsic Gox lifetime, and thus a longer intrinsic Gox lifetime under used blocking condition (e.g. 800V) therefore can be achieved, as indicated by the red arrow. It is recommended that should be extracted by conducting TDDB tests at multiple voltages on the same group of devices whenever possible. Fig. 4(b) predicts MTTF for various stress voltages, values ranging from 1200 V to 1400 V with a value of hours and a value of 1 . With no failures in any of the three voltage scenarios values are extracted using Eq. 1, as shown by the yellow circles at and 1400 V . MTTF lines are drawn by connecting the value to the yellow dots. The model predicts that devices with no failures at 1400 V will have a longer MTTF lifetime under operating conditions compared to those with no failures at 1200 V , as indicated by the red arrow. Figure 4(c) illustrates the effect of increasing sample size on the lifetime plot, assuming zero failures in all cases. It is important to note here that a higher sample size does not necessarily lead to a proportionate increase in lifetime estimate under operating condition, as values remain constant at hours in this scenario. Finally, Fig. 4(d) shows the impact of different Weibull values, ranging from 1 to 2 , on lifetime projections. In case of ARB, the Weibull value should be validated with a longer test, as the value under blocking conditions may differ from that of gate bias-mediated TDDB test, especially since hot holes could contribute to the failure mechanism under ARB, as mentioned in Ref. [4].

Fig. 4. MTTF ( ) lifetime plots are presented based on assumptions that 0 fails have been encountered after 1000 hours of stressing with (a) varying from to hours, , , sample size parts (b) three different stress conditions ranging from 1200-1400 V, hours, , sample size parts (c) variable sample sizes ranging from 240 to 1000, hours, , (d) varying from 1 to 2 while hours and sample size .

Fig. 4. MTTF ( ) lifetime plots are presented based on assumptions that 0 fails have been encountered after 1000 hours of stressing with (a) varying from to hours, , , sample size parts (b) three different stress conditions ranging from 1200-1400 V, hours, , sample size parts (c) variable sample sizes ranging from 240 to 1000, hours, , (d) varying from 1 to 2 while hours and sample size .

Shortcomings of this Method

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Fig. 5 shows certain shortcomings of this technique to project Gox lifetime under blocking from a single point data set. Consideration has been given to scenarios where blocking lifetime estimated from TDDB extracted value predicts favorable TTF numbers, but lifetime extracted from multiple stress voltages is influenced by an alternative failure mechanism, as shown in Fig. 5(a). In such cases, relying on a single data point may yield an overly optimistic off-state lifetime estimate. However, in such cases the dominant blocking failure mechanism likely will be unrelated to intrinsic Gox breakdown and should be tackled in a way beyond the scope of this study. This could be proven by appropriate failure analysis. Conversely, if the TDDB lifetime is adversely affected by a mechanism other than intrinsic Gox failures, then by virtue of lower value, the blocking lifetime estimation might get impacted and will project a rather pessimistic value. So, it is imperative to make sure that the value estimated from TDDB represents true intrinsic Gox failure mechanism. Interested readers may review Ref. [4] for a modeling work where extrinsic defects have been introduced to perform a defect mediated lifetime modeling under blocking conditions. Finally, this
paper focuses on the off-state reliability under stress with gate grounded. Similar analysis is possible for scenarios where negative (for n -channel MOSFET) works in tandem with for assessing blocking reliability.

Fig. 5. Scenarios when using values from a TDDB test. a) Failure mechanism not related to intrinsic Gox breakdown, in which estimated lifetime is overly optimistic compared to full analysis with multiple stress voltages, b) Poor value estimated from TDDB for failures likely not related to intrinsic Gox breakdown can result a rather pessimistic blocking lifetime prediction.

Fig. 5. Scenarios when using values from a TDDB test. a) Failure mechanism not related to intrinsic Gox breakdown, in which estimated lifetime is overly optimistic compared to full analysis with multiple stress voltages, b) Poor value estimated from TDDB for failures likely not related to intrinsic Gox breakdown can result a rather pessimistic blocking lifetime prediction.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1022.83.pdf

In conclusion, we present a novel alternative modeling technique to project MOSFET intrinsic Gox lifetime under blocking from a single drain bias stress dataset with the aid of TDDB results done on a similar group of devices at the same temperature which is otherwise extremely time consuming or even impossible to model.

The authors would like to acknowledge the valuable discussion with J.W. McPherson in this regard.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.83.pdf

J. W. Palmour, L. Cheng, V. Pala, E. Van Brunt, D. J. Lichtenwalner, G-Y Wang, J. Richmond, M. O'Loughlin, S.-H. Ryu, S. T. Allen, A. A. Burk and C. Scozzie, Silicon Carbide Power MOSFETs: Breakthrough Performance from 900 V up to 15 kV , IEEE International Symposium on Power Semiconductor Device & IC's (ISPSD), (2014) 79-82.

D. A. Gajewski, B. Hull, D. J. Lichtenwalner, S.-H. Ryu, E. Bonelli, H. Mustain, G-Y Wang, S. T. Allen and J. W. Palmour, SiC Power Device Reliability, IEEE International Integrated Reliability Workshop, (2016) 29-34.

D. J. Lichtenwalner, S. Sabri, E. V. Brunt, B. Hull, S.-H. Ryu, P. Steinmann, A. Romero, S. Ganguly, D. A. Gajewski, S. Allen and J. W. Palmour, Accelerated Testing of SiC Power Devices, IEEE International Integrated Reliability Workshop, (2020) 1-6.

E. Van Brunt, D. J. Lichtenwalner, J. H. Park, S. Ganguly and J. W. McPherson, Lifetime Modeling of the MOS Interface in the HTRB Condition Under the Influence of Screw Dislocations, IEEE International Reliability Physics Symposium (IRPS), (2023) 1-7.

P. Moens, F. Geenen, M. Avramenko and G. Gomez-Garcia, On the Intrinsic and Extrinsic Reliability Challenges of SiC MOSFETs, IEEE International Reliability Physics Symposium (IRPS), (2024) 1-7.

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