Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 13-20

doi: 10.4028/p-fG2SXX

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-18

Accepted:
2025-08-27

Online:
2025-09-10

A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Jihun Lim , Arman Ur Rashid , Britt Brooks , and Sei-Hyung Ryu

Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

a*jihun.lim@wolfspeed.com, armanur.Rashid@wolfspeed.com, britt.Brooks@wolfspeed.com, sei-hyung.ryu@wolfspeed.com

Keywords: power MOSFET, SPICE simulation, physics-based modeling, switching behavior, TCAD

Abstract

Wide-bandgap silicon carbide (SiC) devices have shown great promise in power control systems due to its high efficiency and thermal stability. However, the absence of predictive compact models for SiC MOSFETs has hindered the validation of these benefits in power electronics applications through circuit simulations. To address this challenge, we introduce a physics-based SPICE model (PbSM) for SiC vertical power MOSFETs. This model is composed of basic subcircuit components that represent various regions in the MOSFET structure, which are physically modeled using a technology computer-aided design (TCAD) tool. By incorporating parasitic resistors into the PbSM, we incorporate the body effect within the MOS channel model with four terminals, thereby enhancing the capability of SPICE simulations. We include theoretical output ( ) and reverse transfer capacitances ( ) to simulate transient simulations based on a double-pulse test (DPT) setup. SPICE simulation results for static and dynamic characteristics have excellent agreement with the measured characteristics of a SiC MOSFET device, confirming the capability of the model in switching characteristics with voltage distribution across the multiple components. The PbSM shows the impact of parameter variations in switching performance, which promises valuable insights for modeling of the corner cases. Finally, the PbSM is computationally efficient, showing meaningful competitiveness compared to existing SPICE models for SiC power MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Silicon carbide (SiC) has garnered significant attention in various applications due to its unique physical and electrical properties, including use in heat to electricity conversion [1], high power radiofrequency electronics [2], and power MOSFETs for switching applications [3-5]. Particularly, in the realm of sustainable energy resources, SiC power MOSFETs offers efficient power delivery with distinct advantages such as low leakage current, high efficiency, and electrical stability at high temperatures. A DMOSFET structure facilitates unipolar current operation with the source and drain electrodes vertically across a free-standing SiC substrate [6]. However, the asymmetric structure between the electrodes shows the non-linear potential distribution within the vertical structure, which poses challenges to the applicability of the equations in lateral MOSFET structures.

While empirical compact models can represent device switching behaviors in acceptable manner [7, 8], their reasonability in simulation results remains questionable due to the lack of consideration for the non-linear distribution. This limitation restricts the applicability of these models in SiC power MOSFET circuits, such as DC(AC)-DC converters [9] and motor drives [10].

In this work, we introduce a physics-based SPICE model (PbSM) that includes sub-circuit component models representing the MOS channel, junction field-effect transistor (JFET) region, p-in body diode, capacitors, and parasitic resistors. Using a technology computer aided design (TCAD) tool, we developed the component model structures for the distinct components within a SiC power MOSFET. The MOS channel is modeled using BSIM3 [11], which addresses short channel effects observed in sub-micron channel length ( ). The JFET is represented as a simple resistor, with its resistivity range estimated by considering the junction depletion width ( ) as a function of gate and drain biases. The higher resistivity of p-type SiC compared to p-type Si necessitates the inclusion of p-well resistors in the PbSM, thereby enhancing reverse recovery predictions affected by the body
effect in the MOS channel model. Input, output, and reverse transfer capacitances ( , and , respectively) are modeled based on bias-dependent . The PbSM is validated by comparing static and dynamic behaviors with the measurements from a SiC MOSFET device. Finally, the PbSM demonstrates the capability to simulate and predict circuit behaviors with varying model parameters used in the components.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Low- and High-drain Voltage Operation of a SiC power MOSFET.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 1a) describes the simplified schematic of a SiC power MOSFET, modeled using a TCAD suite. The arrows illustrate the flow of electrons at a turn-on bias condition, passing through the MOS channel, spread (dashed-line arrows), drift (straight solid-line arrows), and substrate. The space charge region (SCR) is generated at the junction, and the is expressed by:

where is the electric charge, is the relative permittivity of is the permittivity of vacuum, and are the carrier concentration in p - and n-type regions, is the built-in potential, and is the bias dropped at the junction. The mainly relies on , which critically controls the conductivity of the spread region, where the current is distributed to the SiC substrate. Under reverse bias to the junction, the expansion of to the substrate reduces the depth of the drift region ( ). Thus, both the spread and drift regions are affected by the , being retreated as a JFET region. The substrate is far away from the edge of , thereby acting as a free-standing resistor. Overall, the electrons travel from the source to drain across different regions, implying that native MOSFET models in SPICE, which traditionally target symmetric planar MOSFETs, are not compatible with the vertical DMOSFET structure.

Fig. 1. a) Cross-section for a SiC power MOSFET. The arrows indicate the flow of electrons when the MOS channel is turned on. G/I: Gate insulator, SCR: Space charge region. b) TCAD simulations for characteristics under and . The gate voltage ( ) varies from 5 to 15 V . The blue box indicates the region of . c) characteristics with extended up to 800 V . The color-shaded regions indicate the enhanced via the increase of temperature in the saturation region. d) Illustration of voltage division ( ) in linear (top) and saturation (bottom) regimes across different regions of MOS channel (Ch), spread, drift, and substrate.

Fig. 1. a) Cross-section for a SiC power MOSFET. The arrows indicate the flow of electrons when the MOS channel is turned on. G/I: Gate insulator, SCR: Space charge region. b) TCAD simulations for characteristics under and . The gate voltage ( ) varies from 5 to 15 V . The blue box indicates the region of . c) characteristics with extended up to 800 V . The color-shaded regions indicate the enhanced via the increase of temperature in the saturation region. d) Illustration of voltage division ( ) in linear (top) and saturation (bottom) regimes across different regions of MOS channel (Ch), spread, drift, and substrate.

Figure 1b) represents the simulated characteristics using the TCAD structure. The gate voltages ( ) range from 7 V to 15 V , and the cell temperatures ( ) vary from to . At 10 V , the applied voltage is primarily dropped across the spread and drift regions. The reciprocal of the slopes determines the on resistance ( ). As increases, also rises due to the increased resistivity in the spread and drift regions. This leads to a positive shift in the boundary between linear and saturation regions. Figure 1c) shows the simulation with extended up to 800 V . In the saturation regime (out of the blue box), is proportional to due to the increase in field-effect mobility ( ) in the MOS channel, which is dominated by the Coulomb scattering near the interface of [12]. The slope of the curve is influenced by channel length modulation ( ) and JFET conductivity.

A steeper slope indicates lower output resistance, ( is the parameter related to the early voltage), resulting in higher sensitivity of to . It affects the operating points and the sharpness of switching on/off states. Thus, understanding CLM and JFET conductance at high is critical for analyzing the transient responses of the MOSFET. Based on the characteristics, Figure 1d) shows the distribution of applied (assuming strong inversion in the MOS channel) across the multiple regions in linear (top) and saturation (bottom) regimes. The ratio of voltage division ( ) across the different regions is strongly dependent on and the operation modes (linear versus saturation), highlighting the importance of interpreting the non-linear voltage distribution in SiC MOSFETs for analyzing their physics-based electrical characteristics.

Fig. 2. a) Schematic of the physics-based SPICE model (PbSM). b) Simulated characteristics of the MOS channel model using the SPICE and TCAD. c) Simulated characteristics of the JFET model using the TCAD. varies from 0 to -40 V , corresponding to the estimated in the MOS channel. The dashed arc arrow indicates the possible resistance (reciprocal of the slope) variation window. The 'turn-off' means zero when the spread region is pinched-off. d) Input ( ), output ( ), and reverse transfer ( ) capacitance models. The capacitances were calculated based on doping concentration and effective device area.

Fig. 2. a) Schematic of the physics-based SPICE model (PbSM). b) Simulated characteristics of the MOS channel model using the SPICE and TCAD. c) Simulated characteristics of the JFET model using the TCAD. varies from 0 to -40 V , corresponding to the estimated in the MOS channel. The dashed arc arrow indicates the possible resistance (reciprocal of the slope) variation window. The 'turn-off' means zero when the spread region is pinched-off. d) Input ( ), output ( ), and reverse transfer ( ) capacitance models. The capacitances were calculated based on doping concentration and effective device area.

SPICE Model with Sub-circuit Components.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 2a) shows the schematic of the PbSM. The MOS channel is modeled using BSIM3, integrated with parasitic resistors ( ) associated with metal contacts and -doped region. A JFET resistor ( ), representing the spread and drift regions, is connected to the MOS channel. The substrate, with relatively high carrier concentration, is modeled as a resistor ( ), which does not significantly influence the impedance of the circuit. The three capacitances - (gate to source), (gate to drain), and (drain to source) - are connected between the electrodes. The p-i-n diode is modeled by the Compact Model Coalition (CMC) diode model [13]. The gate resistor ( ) is connected to the gate and governs the interaction between the gate capacitance and parasitic inductance.

The components in the circuit are modeled using sub-circuit device models derived from a TCAD analysis performed on the SiC power MOSFET structure shown in Fig. 1a). Figure 2b) compares the characteristics of the four-terminal MOS channel device simulated using the TCAD and SPICE tools. The body bias was set to zero. The inset shows the schematic of the TCAD-based MOS channel
structure. The linear region is closely matched between the two models, indicating that the MOS channel model in the SPICE fits the transconductance to the TCAD results. The CLM is sensitive to , contributing to short channel effects such as drain-induced barrier lowering (DIBL), which are captured using key model parameters in BSIM3, as outlined in Table 1.

Table 1. BSIM3 model parameters with the effect on current-voltage characteristics.

Parameters | Effect
ETA0 | DIBL effect coefficient at the subthreshold region
U0, Ua, Ub | Coefficients for the field-effect mobility shape
RDSW | Effect of a parasitic resistance at low Vd
DELTA | Smoothness of the curvatures at non-linear region in Id-Vd
PCLM | Regulation of the early voltage due to channel length modulation
etc. | Other parameters such as VTH0 and doping-relevant values are estimated from the TCAD simulation.

In the saturation region, the is controlled by the model parameters of DELTA and PCLM. Modeling of this variation is important for representing the output conductance ( ) of a SiC MOSFET at high . The threshold voltage ( ) is defined using a model parameter, VTH0, in BSIM3. Physically, is expressed by:

where is the flat-band voltage and is the surface potential, and are the depletion and fixed charges in the MOS channel and gate oxide, respectively. BSIM3 has the limitations in modeling and interface traps, which affect the subthreshold region and not fully represented in BSIM3.

Figure 2c) presents the characteristics of the JFET, with the inset showing a schematic of the TCAD-based JFET, including its electrodes of gate, source, and drain. In this JFET, the potential difference between the source and gate corresponds to the voltage drop across the MOS channel ( ) in the SiC power MOSFET. The TCAD simulation estimates that the can reach up to 40 V . Accordingly, the JFET simulation varies from 0 V to -40 V , resulting in the arc-shaped variation in curves. The amplitude of is limited to less than 1.2 kA , reflecting the meaningful maximum operating current of the SiC power MOSFET, as shown in Fig. 1c). In the SPICE model, the is simplified as the reciprocal of the slope corresponding to in the JFET. However, it is worth noting that using a variable could improve the accuracy of the voltage division in the SPICE simulation.

Figure 2d) illustrates the modeled , , and , which are compared to experimental results using a SiC MOSFET device. As increases, the neutral portion of the spread area is reduced due to the expansion of the by the Eq. (1), leading to a general decrease in due to the reduction of the and . is simply modeled using the Eq. (1). The is composed of the gate oxide ( ) and SiC ( ) capacitances in parallel, expressed as:

where forms across the spread, drift, and substrate. When the becomes large enough to fully occupy the spread and drift regions, kink regions, marked by circles, appear. These kinks are caused by the addition of into , as well as non-linear doping profile across the regions. The overlapped regions between electrodes remain fixed during the simulation. For simplicity,
was set to a constant value, assuming strong inversion in the MOS channel. In a real MOSFET, reaches the threshold voltage, then becomes more crucial in determining the switching performance of the MOSFET, particularly during the gate voltage plateau period [14]. Currently, using a constant does not significantly impact the switching simulation.

SPICE Model Generation for a SiC MOSFET.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 3a) represents the characteristics with ranging from 9 V to 15 V , simulated by the SPICE model (red-dashed lines), and compared to TCAD results (solid lines) and measurements (symbols) for a SiC power MOSFET. The results align closely without significant discrepancies, although the subthreshold region, which is governed by traps at the gate oxide interface, is not yet accurately modeled. Figure 3b) extends the characteristics into the saturation regime, with up to 800 V . Due to power dissipation at high voltage and high current regions, measurements were not performed at this high range and TCAD simulation results were used instead of experimental values. The is unipolar and identical to the current flowing through the MOS channel model. Therefore, the slope at high corresponds to the saturation mode in the MOS channel mode, and balancing the voltage division in the PbSM is important for controlling the operation points. It is important to note that in the saturation region determines the sensitivity of and the sharpness of the transient response. This indicates that the modeling of as a function of remains a topic for future work. Figure 3c) shows the at the third quadrant, where the current paths through the body diode or MOS channel are precisely modeled to match the measurements. As discussed earlier, the subthreshold region in the MOS channel is not properly modeled yet, resulting in the mismatch at a . In addition, the reverse recover charges ( ) and time ( )are empirically modeled [13] at a .

Fig. 3. a) Simulated characteristics using the PbSM in the linear region, compared to the TCAD and measurements using a SiC MOSFET. b) Simulated characteristics of the PbSM with the extended up to 800 V , compared to the TCAD. c) Simulated characteristics of the PbSM , compared to the measurement. d) Double-pulse test (DPT) simulations (dashed lines) compared to measurements (symbols). The top and bottom graphs indicate the turn-on and turn-off status, respectively.

Fig. 3. a) Simulated characteristics using the PbSM in the linear region, compared to the TCAD and measurements using a SiC MOSFET. b) Simulated characteristics of the PbSM with the extended up to 800 V , compared to the TCAD. c) Simulated characteristics of the PbSM , compared to the measurement. d) Double-pulse test (DPT) simulations (dashed lines) compared to measurements (symbols). The top and bottom graphs indicate the turn-on and turn-off status, respectively.

Figure 3d) presents the transient performance of turn-on (top) and turn-off (bottom) from the SPICE simulation (solid line) and measurement (symbols) using the MOSFET. The dynamic switching behavior was characterized through a Double-Pulse Test (DPT) [15]. The DPT simulation was conducted using a circuit that includes the MOSFET SPICE model along with the parasitic components from the DPT setup [16]. The SPICE results closely match the measurements, including the increase in drain current with each subsequent gate pulse. The and values are very wellmatched, meaning the reasonable design of key factors such as , and . The measurement was conducted at , with the effect of reverse recovery considered negligible.

SPICE Corner Models via Parameter Variations.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 4a) illustrates the generation of several SPICE models based on device parameter variations implemented in the PbSM . The turn on/off regions are particularly sensitive to these variations and the voltage division ratio among the different components. Figure 4b) shows the impact of device parameters on and . For example, a reduction of shortens the charging time, resulting in faster switching characteristics and decreased energy losses. An increase in requires a higher and lowers the switching speed, leading to an increase in , but conversely, a decrease in . These are directly influenced by manufacturing processes such as gate oxide thickness, ion implantation, and other critical dimensions. The PbSM captures the trend of energy loss variations based on these process variations. Using the DPT method, Figure 4c) demonstrates the turn-on (top) and turn-off (bottom) characteristics. It assumes the variation of the width in the spread region ( ), changing with an arbitrary variation range of . Compared to the turn-on, the discharging amount between the drain to source and gate becomes more important in the turn-off, and it results in the noticeable positive or negative shifts.

Fig. 4. a) Illustration of the impact of device parameter variations in the and different model generations. b) Impact of the parameters on and c) Example of switching performance variations via the change ( ) in the width in the spread region ( ). The simulation used the same DPT method in Fig. 3c), which are represented by the color contours. d) Change of the relative energy loss ( ) during the transient time in c ). The arrows mean the regions of on, conduction, and off status.

Fig. 4. a) Illustration of the impact of device parameter variations in the and different model generations. b) Impact of the parameters on and c) Example of switching performance variations via the change ( ) in the width in the spread region ( ). The simulation used the same DPT method in Fig. 3c), which are represented by the color contours. d) Change of the relative energy loss ( ) during the transient time in c ). The arrows mean the regions of on, conduction, and off status.

Figure 4d) illustrates the change of the relative energy loss ( ) during the transient time. It intuitively indicates reduced energy loss with a lower . The PbSM shows high sensitivity via individual parameter variations on switching performance. However, the relationships between different parameters are uncertain (can be strongly correlated or orthogonal), which can either amplify or counterbalance the min-max ranges in corner cases. Therefore, analyzing statistical data from manufacturing is crucial to reveal the correlations between device parameters and to project the corner models using the PbSM for SiC MOSFETs.

Evaluation of Computational Efficiency.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Table 2 presents a performance comparison between the existing model currently available on Wolfspeed website [17], which is more behavioral with empirical fitting, and the PbSM a SiC for power MOSFET. The test circuit is a interleaved boost converter, and transient simulation analysis was performed with a total circuit run time of 50 milliseconds using LTSpice. The circuit details are provided in the previous result [18]. Compared to the existing model, the iteration numbers for transient analysis decreased by approximately . The total number of transient points evaluated increased by about . Therefore, the computation points were not significantly different between the models. Notably, the clock time for the PbSM is only about higher than the behavioral model, indicating a relatively small computational penalty for additional capability of representing physical variability of the PbSM .

Table 2. Comparison of SPICE simulation computation between a previous model and PbSM .

Test items | PbSM | Existing model [18]
Total number of Newton iterations | 219,313,034 | 299,618,943
Iteration numbers for transient analysis | 219,313,024 | 299,618,933
Transient points evaluated | 105,924,496 | 109,740,265
Clock time | 5.1 hours | 3.2 hours

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

This work presents a SPICE model, named PbSM, for SiC power MOSFETs, designed using physics-based sub-circuit components such as the MOS channel, JFET, and parasitic resistors. The sub-micron is primarily modeled using BSIM3, which controls the onset of Miller plateau region. The JFET, representing the spread and drift regions, is currently modeled as a constant resistor, which does not compromise accuracy of switching simulations. The PbSM effectively distributes the applied voltage across the different components, aiding in the understanding of key model parameters that determines the characteristics. Physics-based and closely match measurements from a SiC MOSFET device, which are important for designing turn-on/off states. The PbSM simulations depict characteristics, with the linear region validated through comparison with measurements. Though the saturation region falls beyond the scope of validation, we identify that CLM and JFET conductivity are critical for regulating . A DPT circuit, designed using the PbSM, simulates switching behaviors that align closely with measurements across the turn on, conduction, and turn off regions. The PbSM is capable of tracking trends in physics-based variations of energy losses via parameter changes, paving the way for the generation of corner models that accounts for manufacturing process variations. Finally, we propose this model with the enhanced representations of device physics, providing a powerful tool for further investigation of SiC power MOSFET applications.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

. Lim, J., et al., Enhanced Photon Utilization in Single Cavity Mode Air-Bridge Thermophotovoltaic Cells. ACS Energy Letters, 2023. 8: p. 2935-2939.

. Pribble, W., et al. Applications of SiC MESFETs and GaN HEMTs in power amplifier design. in 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No. 02CH37278). 2002. IEEE.

. Sabri, S., et al. New generation 6.5 kV SiC power MOSFET. in 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA). 2017. IEEE.

. Gajewski, D.A., et al. SiC power device reliability. in 2016 IEEE International Integrated Reliability Workshop (IIRW). 2016. IEEE.

. Cooper, J.A., et al., Status and prospects for SiC power MOSFETs. IEEE Transactions on Electron Devices, 2002. 49(4): p. 658-664.

. Hsu, F.-J., et al. High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier. in 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). 2017. IEEE.

. Arribas, A.P., et al., Simple and accurate circuit simulation model for SiC power MOSFETs. IEEE Transactions on Electron Devices, 2015. 62(2): p. 449-457.

. McNutt, T., et al., Compact models for silicon carbide power devices. Solid-State Electronics, 2004. 48(10-11): p. 1757-1762.

. Shen, Z.J., SiC research beyond power MOSFET: What's next?[Happenings]. IEEE Power Electronics Magazine, 2021. 8(2): p. 14-23.

. Stella, F., et al. Advanced testing of SiC power MOSFET modules for electric motor drives. in 2017 IEEE International Electric Machines and Drives Conference (IEMDC). 2017. IEEE.

. Cheng, Y. and C. Hu, MOSFET modeling & BSIM3 user's guide. 1999: Springer Science & Business Media.

. Pérez-Tomás, A., et al., Field-effect mobility temperature modeling of metal-oxidesemiconductor transistors. Journal of applied physics, 2006. 100(11).

. Rashid, A.U., et al. Modeling of the Snappy, and Soft Reverse Recovery of SiC MOSFET's Body Diode. in 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). 2023. IEEE.

. Baliga, B.J., Fundamentals of power semiconductor devices. 2010: Springer Science & Business Media.

. Porpora, F., et al. Accurate Data-Driven Losses Modeling for SiC-Based Converters. in 2024 IEEE Applied Power Electronics Conference and Exposition (APEC). 2024. IEEE.

. SpeedVal Kit Half-Bridge Motherboard User Guide. Available from: rboard_User_Guide.pdf.

. Moxey, G. Modeling common topologies with Wolfspeed Silicon Carbide MOSFETs. Available from: .

. 100 KHZ 10KW Interleaved Boost Converter with full SiC MOSFET. Available from: roverview.pdf

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.